- 25 Jul, 2022 40 commits
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Rodrigo Siqueira authored
When we use the allmodconfig option we see the following error: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In function 'dml32_ModeSupportAndSystemConfigurationFull': drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3799:1: error: the frame size of 2464 bytes is larger than 2048 bytes [-Werror=frame-larger-than=] 3799 | } // ModeSupportAndSystemConfigurationFull This commit fixes this issue by moving part of the mode support operation from ModeSupportAndSystemConfigurationFull to a dedicated function. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Tested-by:
Stephen Rothwell <sfr@canb.auug.org.au> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Anthony Koo authored
This version brings along following fixes: - Copy crc_skip_count when duplicating CRTC state - Add debug option for idle optimizations on cursor updates - Disable MPC split for DCN32/321 - Add missing ODM 2:1 policy logic - Update DCN32 and DCN321 SR latencies - Add reinstate dram in the FPO logic - Add dc_ctx to link_enc_create() parameters - Cache cursor when cursor exceeds 64x64 - Add support for manual DMUB FAMS trigger - Fix dpstreamclk programming - Add missing AUDIO_DTO_SEL reg field - Add OTG/ODM functions - Use correct clock source constructor for DCN314 - Use correct DTO_SRC_SEL for 128b/132b encoding - Add pixel rate div calcs and programming - Remove FPU flags from DCN30 Makefile - Create patch bounding box function for isolate FPU - Move mclk calculation function to DML - Remove FPU operations from dcn201 resources - Fallback to SW cursor if SubVP + cursor too big - Drop unnecessary FPU flags on dcn302 files - Reboot while unplug hdcp enabled dp from mst hub - Reset pipe count when iterating for DET override - Calculate MALL cache lines based on Mblks required - Fix two MPO videos in single display ODM combine mode - Guard against zero memory channels - Updates SubVP + SubVP DRR cases updates - Fix OPTC function pointers for DCN314 - Add enable/disable FIFO callbacks to stream setup - Avoid MPC infinite loop Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Leo Li authored
[Why] crc_skip_count is used to track how many frames to skip to allow the OTG CRC engine to "warm up" before it outputs correct CRC values. Experimentally, this seems to be 2 frames. When duplicating CRTC states, this value was not copied to the duplicated state. Therefore, when this state is committed, we will needlessly wait 2 frames before outputing CRC values. Even if the CRC engine is already warmed up. [How] Copy the crc_skip_count as part of dm_crtc_duplicate_state. Acked-by:
Leo Li <sunpeng.li@amd.com> Tested-by:
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Alvin Lee authored
For optimizations and debug purposes we added an option to exit idle operations on cursor updates. Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Alvin Lee authored
Due to CRB, no need to rely on MPC splitting to maximize use of DET anymore. Reviewed-by:
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Samson Tam authored
Phantom pipes must use the same configuration used in main pipes. This commit add this check. Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
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Alvin Lee authored
Update worst case SR latencies according to values measured by hardware team. Reviewed-by:
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Rodrigo Siqueira authored
In order to handle FPO correctly, we need to reinstate the dram values. This function adds the required code to handle the vblank stretch and the dram calculation. Acked-by:
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Aurabindo Pillai authored
[Why&How] Preparation to enable run time initialization of register offsets to add dc_context to the link_enc_create callback. This is needed to get the dc_ctx handle where register offset initialization routine is called. Reviewed-by:
Alan Liu <HaoPing.Liu@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Chris Park authored
[Why] When Static screen from MALL, the cursor needs to be cached if cursor exceeds 64x64 size. [How] Program the bit that cache cursor in MALL when size of the cursor exceeds 64x64. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Chris Park <chris.park@amd.com> Tested-by:
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Anthony Koo authored
- Add is_drr parameter to indicate DRR is enabled on the panel to determine whether SubVP MCLK switch logic should be enabled - Add DRR manual trigger in FW (instead of driver) because manual trigger programming triggers DRR update pending and can block SubVP MCLK switches from taking place Acked-by:
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Michael Strauss authored
[WHY] Currently programming incorrect hpo inst as well as selecting incorrect source [HOW] Use hpo inst instead of otg inst to select dpstreamclk inst Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Needed to program audio dto Reviewed-by:
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Michael Strauss authored
[WHY] Required for correct OTG_H_TIMING_CNTL programming Reviewed-by:
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Michael Strauss authored
[WHY] Previously was pointing to DCN3 clock constructor rather than DCN31's Reviewed-by:
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Michael Strauss authored
[WHY] DP DTO isn't used for 128b/132b encoding [HOW] Check current link rate to determine whether using 8b/10b or 128/132b encoding Reviewed-by:
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Michael Strauss authored
[WHY/HOW] Need to calculate and set some pixel rate divisors on correct otg_inst Reviewed-by:
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Rodrigo Siqueira authored
At this stage, we must have all the FPU code for DCN30 isolated in the DML folder. Drop FPU flags from Makefile. Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Rodrigo Siqueira authored
In the DCN30 resource, we have a small patch to the bounding box struct; this patch uses FPU operations. This commit moves that specific part to its function under the DML folder. Reviewed-by:
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Rodrigo Siqueira authored
The function responsible for calculating the MCLK switching has FPU operations. This commit moves it to the dcn30_fpu file. Reviewed-by:
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Rodrigo Siqueira authored
We have some FPU operations on the resource part of the DCN201. This commit drops FPU flags and moves any required FPU code to the DML folder. Reviewed-by:
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Alvin Lee authored
[Description] - For SubVP cursor cannot be cached in MALL, therefore we will switch to SW cursor if the cursor size exceeds what can fit in the local DCN buffers (64x64x4) - Returning false / failure for set_cursor_attributes will fallback to SW cursor Reviewed-by:
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Rodrigo Siqueira authored
We already isolated the DCN302 code in the DML folder, but we forgot to drop the FPU flags from the Makefile. This commit drops those flags. Reviewed-by:
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hersen wu authored
[Why] event_property_update does not check NULL pointer [How] check aconnector->base.state equals NULL Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
hersen wu <hersenxs.wu@amd.com> Tested-by:
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Taimur Hassan authored
[Why] Coding error in DET allocation was resulting in too few DET segments being allocated, causing underflow. [How] Reset pipe count each time we begin iterating through pipes for a stream. Reviewed-by:
Taimur Hassan <Syed.Hassan@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Calculation for NumWays in MALL should be based on number of MBlks Reviewed-by:
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Samson Tam authored
[Why] In single display ODM combine mode, two MPO videos ( three planes ) are not working [How] When we detect three planes, don't set odm combine 2to1 policy for the MPO planes. Otherwise, we run out of pipes available Add support for two MPO videos in dc_add_plane_to_context(). Don't allow both videos to be on the same side of the display. Add extra check when fetching free pipe for two MPO videos. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] If BIOS doesn't specify number of memory channels then bandwidth validation will fail due to insufficient BW in DML. [How] If BIOS is setting zero channels then use the default in the table. If no entry is in the table and no BIOS value is specified then throw an ASSERT for future developers to look into. Reviewed-by:
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Alvin Lee authored
[Description] - For any DRR cases in SubVP, don't lock for VSYNC flips - For DCN32/321 use FW to do DRR manual trigger programming - Add bit in SubVP cmd to indicate if the SubVP pipe is DRR Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Access violation occurs when swapping between HDMI and FRL monitors because we're missing the immediate_disable_crtc callback and it's required for the DCN314 clk manager. [How] Update the table to match the DCN31 optc functions for ones that should be the same: - immediate_disable_crtc - configure_crc Reviewed-by:
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Nicholas Kazlauskas authored
[Why] We don't write out attributes after disabling and re-enabling the link on some monitors, causing some, but not all, HDMI displays to fail to lightup on DCN314. [How] Firmware used to do this after DIG link setup. Since firmware is no longer doing this to support USB4 and dynamic link remapping we'll need to add this to driver in the equivalent paths. New optional callbacks were created in the stream encoder interface and implementations were added for DCN314. Reviewed-by:
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Aric Cyr authored
[why] In some cases MPC tree bottom pipe ends up point to itself. This causes iterating from top to bottom to hang the system in an infinite loop. [how] When looping to next MPC bottom pipe, check that the pointer is not same as current to avoid infinite loop. Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Aaron Liu authored
Enable swiotlb for gmc 11.0. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Aaron Liu authored
Enable swiotlb for gmc 10.0. v2: include drm_cache.h to use the function ‘drm_need_swiotlb’ Signed-off-by:
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Slark Xiao authored
Replace 'the the' with 'the' in the comment. Signed-off-by:
Slark Xiao <slark_xiao@163.com> Signed-off-by:
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Alex Deucher authored
Move stack variables to dummy structure. Reviewed-by:
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Alex Deucher authored
Move stack variables to dummy structure. Reviewed-by:
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Alex Deucher authored
Move stack variables to dummy structure. Reviewed-by:
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Alex Deucher authored
Move stack variables to dummy structure. Reviewed-by:
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Alex Deucher authored
Move additional dummy structures off the stack and into the dummy vars structure. Fixes the following: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In function 'DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation': drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1659:1: error: the frame size of 2144 bytes is larger than 2048 bytes [-Werror=frame-larger-than=] 1659 | } | ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In function 'dml32_ModeSupportAndSystemConfigurationFull': drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3799:1: error: the frame size of 2464 bytes is larger than 2048 bytes [-Werror=frame-larger-than=] 3799 | } // ModeSupportAndSystemConfigurationFull | ^ v2: move more stuff to dummy structure, fix init order (Alex) Acked-by:Christian König <christian.koenig@amd.com> Reviewed-by:
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