- 12 Jul, 2019 2 commits
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Stephen Boyd authored
Merge branches 'clk-qcom-gdsc-warn', 'clk-ingenic', 'clk-qcom-qcs404-reset', 'clk-xgene-limit' and 'clk-meson' into clk-next * clk-qcom-gdsc-warn: clk: qcom: gdsc: WARN when failing to toggle * clk-ingenic: MIPS: Remove dead code clk: ingenic: Remove unused functions MIPS: jz4740: PM: Let CGU driver suspend clocks and set sleep mode clk: ingenic: Handle setting the Low-Power Mode bit clk: ingenic: Add missing header in cgu.h clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly clk: ingenic/jz4725b: Fix incorrect dividers for main clocks clk: ingenic/jz4770: Fix incorrect dividers for main clocks clk: ingenic/jz4740: Fix incorrect dividers for main clocks clk: ingenic: Add support for divider tables * clk-qcom-qcs404-reset: clk: gcc-qcs404: Add PCIe resets * clk-xgene-limit: clk: xgene: Don't build COMMON_CLK_XGENE by default * clk-meson: clk: meson: g12a: mark fclk_div3 as critical clk: meson: g12a: Add support for G12B CPUB clocks dt-bindings: clk: meson: add g12b periph clock controller bindings clk: meson-g12a: add temperature sensor clocks dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs clk: meson: meson8b: add the cts_i958 clock clk: meson: meson8b: add the cts_mclk_i958 clocks clk: meson: meson8b: add the cts_amclk clocks dt-bindings: clock: meson8b: add the audio clocks clk: meson: g12a: add controller register init clk: meson: eeclk: add init regs clk: meson: g12a: add mpll register init sequences clk: meson: mpll: add init callback and regs clk: meson: axg: spread spectrum is on mpll2 clk: meson: gxbb: no spread spectrum on mpll0 clk: meson: mpll: properly handle spread spectrum clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo
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Stephen Boyd authored
Merge branches 'clk-pwm-duty', 'clk-bcm', 'clk-mtk', 'clk-qcom-msm8998-gpu' and 'clk-renesas' into clk-next - Add support to get duty cycle of generic pwm clks * clk-pwm-duty: clk: pwm: implement the .get_duty_cycle callback * clk-bcm: clk: bcm: Allow CLK_BCM2835 for ARCH_BRCMSTB clk: bcm: Make BCM2835 clock drivers selectable * clk-mtk: clk: mediatek: Remove MT8183 unused clock clk: mediatek: add audsys clock driver for MT8516 dt-bindings: mediatek: audsys: add support for MT8516 * clk-qcom-msm8998-gpu: dt-bindings: clock: Document gpucc for msm8998 * clk-renesas: clk: renesas: cpg-mssr: Use [] to denote a flexible array member clk: renesas: cpg-mssr: Combine driver-private and clock array allocation clk: renesas: mstp: Combine group-private and clock array allocation clk: renesas: div6: Combine clock-private and parent array allocation clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv clk: renesas: r8a774a1: Add TMU clock clk: renesas: r8a77995: Add CMM clocks clk: renesas: r8a77990: Add CMM clocks clk: renesas: r8a77965: Add CMM clocks clk: renesas: r8a7795: Add CMM clocks clk: renesas: r9a06g032: Add clock domain support dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains clk: renesas: mstp: Remove error messages on out-of-memory conditions clk: renesas: cpg-mssr: Remove error messages on out-of-memory conditions clk: renesas: cpg-mssr: Use genpd of_node instead of local copy clk: renesas: r8a7796: Add CMM clocks clk: renesas: r8a779{5|6|65}: Add TPU clock
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- 25 Jun, 2019 7 commits
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Paul Cercueil authored
Remove the unused <asm/mach-jz4740/clock.h> include. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Acked-by:
Paul Burton <paul.burton@mips.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Paul Cercueil authored
These functions are not called anywhere anymore, they can safely be removed. Signed-off-by:
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Paul Cercueil authored
Instead of forcing the jz4740 clocks to suspend here, we let the CGU driver handle it. We also let the CGU driver set the "sleep mode" bit. This has the added benefit that now it is possible to build a kernel on SoCs newer than the JZ4740 with CONFIG_PM. Signed-off-by:
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Paul Cercueil authored
The Low-Power Mode, when enabled, will make the "wait" MIPS instruction suspend the system. This is not really clock-related, but this bit happens to be in the register set of the CGU. Signed-off-by:
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Paul Cercueil authored
The cgu.h has structures that contain 'clk_onecell_data' and 'clk_hw' structures (no pointers), so the <linux/clk-provider.h> header should be included. Signed-off-by:
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v5.3-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add CMM (Color Management Module) clocks on R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on RZ/G2M - Small cleanups and fixes * tag 'clk-renesas-for-v5.3-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Use [] to denote a flexible array member clk: renesas: cpg-mssr: Combine driver-private and clock array allocation clk: renesas: mstp: Combine group-private and clock array allocation clk: renesas: div6: Combine clock-private and parent array allocation clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv clk: renesas: r8a774a1: Add TMU clock clk: renesas: r8a77995: Add CMM clocks clk: renesas: r8a77990: Add CMM clocks clk: renesas: r8a77965: Add CMM clocks clk: renesas: r8a7795: Add CMM clocks
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https://github.com/BayLibre/clk-mesonStephen Boyd authored
Pull Amlogic clk driver updates from Jerome Brunet: - Fix mpll fractional part and spread sprectrum issues - Add meson8 audio clocks - Add g12a temperature sensors clocks - Add g12a and g12b cpu clocks * tag 'clk-meson-5.3-1' of https://github.com/BayLibre/clk-meson: clk: meson: g12a: mark fclk_div3 as critical clk: meson: g12a: Add support for G12B CPUB clocks dt-bindings: clk: meson: add g12b periph clock controller bindings clk: meson-g12a: add temperature sensor clocks dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs clk: meson: meson8b: add the cts_i958 clock clk: meson: meson8b: add the cts_mclk_i958 clocks clk: meson: meson8b: add the cts_amclk clocks dt-bindings: clock: meson8b: add the audio clocks clk: meson: g12a: add controller register init clk: meson: eeclk: add init regs clk: meson: g12a: add mpll register init sequences clk: meson: mpll: add init callback and regs clk: meson: axg: spread spectrum is on mpll2 clk: meson: gxbb: no spread spectrum on mpll0 clk: meson: mpll: properly handle spread spectrum clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo
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- 20 Jun, 2019 5 commits
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Geert Uytterhoeven authored
Flexible array members should be denoted using [] instead of [0], else gcc will not warn when they are no longer at the end of the structure. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Make cpg_mssr_priv.clks[] a flexible array member, and use the new struct_size() helper, to combine the allocation of the driver-private structure and array of available clocks. Signed-off-by:
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Geert Uytterhoeven authored
Make mstp_clock_group.clks[] a flexible array member, and use the new struct_size() helper, to combine the allocation of the group-private structure and array of module clocks. Signed-off-by:
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Geert Uytterhoeven authored
Make div6_clock.parents[] a flexible array member, and use the new struct_size() helper, to combine the allocation of the clock-private structure and array of parent clocks. Signed-off-by:
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Geert Uytterhoeven authored
New fields were added, but kerneldoc was forgotten, or inserted at the wrong place. Signed-off-by:
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- 18 Jun, 2019 5 commits
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Fabrizio Castro authored
This patch adds the TMU clocks to the R8A774A1 SoC. Signed-off-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
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Jacopo Mondi authored
Add clock definitions for CMM units on Renesas R-Car D3. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Jacopo Mondi authored
Add clock definitions for CMM units on Renesas R-Car E3. Signed-off-by:
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Jacopo Mondi authored
Add clock definitions for CMM units on Renesas R-Car M3-N. Signed-off-by:
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Jacopo Mondi authored
Add clock definitions for CMM units on Renesas R-Car H3. Signed-off-by:
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- 12 Jun, 2019 1 commit
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Marc Gonzalez authored
Building COMMON_CLK_XGENE is pointless, unless we're building for an XGENE system. Signed-off-by:
Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by:
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- 11 Jun, 2019 12 commits
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Neil Armstrong authored
On Amlogic Meson G12b platform, the fclk_div3 seems to be necessary for the system to operate correctly. Disabling it cause the entire system to freeze, including peripherals. Let's mark this clock as critical, fixing boot on G12b platforms. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com>
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Neil Armstrong authored
Update the Meson G12A Clock driver to support the Amlogic G12B SoC. G12B clock driver is very close, the main differences are : - the clock tree is duplicated for the both clusters, and the SYS_PLL are swapped between the clusters - G12B has additional clocks like for CSI an other components Here only the cpu clock tree is handled. Reviewed-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
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Jerome Brunet authored
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Neil Armstrong authored
Update the documentation to support clock driver for the Amlogic G12B SoC. G12B clock driver is very close, the main differences are : - the clock tree is duplicated for the both clusters, and the SYS_PLL are swapped between the clusters - G12B has additional clocks like for CSI an other components Reviewed-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Guillaume La Roque authored
Add the TS clocks used by two temperature sensors Reviewed-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com> Signed-off-by:Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [fixed commit description]
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Jerome Brunet authored
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Guillaume La Roque authored
Add clock ids used by the temperature sensors of the G12A Socs Reviewed-by:
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Martin Blumenstingl authored
Add the cts_i958 clock to control the clock source of the spdif output block. It is used to select whether the clock source of the spdif output is cts_amclk (when data are taken from i2s buffer) or the cts_mclk_i958 (when data are taken from the spdif buffer). The setup for this clock is identical to GXBB, so this ports commit 7eaa44f6 ("clk: meson: gxbb: add cts_i958 clock") to the Meson8/Meson8b/Meson8m2 clock driver. Signed-off-by:
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Martin Blumenstingl authored
Add the SPDIF master clock also referred as cts_mclk_i958. The setup for this clock is identical to GXBB, so this ports commit 3c277c24 ("clk: meson: gxbb: add cts_mclk_i958") to the Meson8/Meson8b/Meson8m2 clock driver. Signed-off-by:
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Martin Blumenstingl authored
Add the I2S master clock also referred as cts_amclk. The setup for this clock is identical to GXBB, so this ports commit 4087bd4b ("clk: meson: gxbb: add cts_amclk") to the Meson8/Meson8b/Meson8m2 clock driver. Signed-off-by:
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Jerome Brunet authored
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Martin Blumenstingl authored
The audio controllers on Meson8, Meson8b and Meson8m2 use similar (potentially the same) audio clocks as GXBB, GXL and GXM. Add the CLKID_CTS_AMCLK, CLKID_CTS_MCLK_I958 and CLKID_CTS_I958 clock IDs so they can be used for the audio controllers. Signed-off-by:
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- 07 Jun, 2019 8 commits
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Bjorn Andersson authored
Enabling PCIe requires several of the PCIe related resets from GCC, so add them all. Reviewed-by:
Niklas Cassel <niklas.cassel@linaro.org> Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Bjorn Andersson authored
Failing to toggle a GDSC as the driver core is attaching the power-domain to a device will cause a silent probe deferral. Provide an explicit warning to the developer, in order to reduce the amount of time it takes to debug this. Signed-off-by:
Jeffrey Hugo <jhugo@codeaurora.org> Tested-by:
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Paul Cercueil authored
The code was setting the bit 21 of the CPCCR register to use a divider of 2 for the "pll half" clock, and clearing the bit to use a divider of 1. This is the opposite of how this register field works: a cleared bit means that the /2 divider is used, and a set bit means that the divider is 1. Restore the correct behaviour using the newly introduced .div_table field. Signed-off-by:
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Paul Cercueil authored
The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by:
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Paul Cercueil authored
The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by:
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Paul Cercueil authored
The main clocks (cclk, hclk, pclk, mclk, lcd) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by:
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Paul Cercueil authored
Some clocks provided on Ingenic SoCs have dividers, whose hardware value as written in the register cannot be expressed as an affine function to the actual divider value. For instance, for the CPU clock on the JZ4770, the dividers are coded as follows: ------------------ | Bits | Div | ------------------ | 0 0 0 | 1 | | 0 0 1 | 2 | | 0 1 0 | 3 | | 0 1 1 | 4 | | 1 0 0 | 6 | | 1 0 1 | 8 | | 1 1 0 | 12 | ------------------ To support this setup, we introduce a new field in the ingenic_cgu_div_info structure that allows to specify the divider table. Signed-off-by: -
Stephen Boyd authored
Merge tag 'clk-renesas-for-v5.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add TPU (Timer Pulse Unit / PWM) clocks on R-Car H3, M3-W, and M3-N - Add CMM (Color Management Module) clocks on R-Car M3-W - Add Clock Domain support on RZ/N1 * tag 'clk-renesas-for-v5.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a06g032: Add clock domain support dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains clk: renesas: mstp: Remove error messages on out-of-memory conditions clk: renesas: cpg-mssr: Remove error messages on out-of-memory conditions clk: renesas: cpg-mssr: Use genpd of_node instead of local copy clk: renesas: r8a7796: Add CMM clocks clk: renesas: r8a779{5|6|65}: Add TPU clock
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