- 15 Nov, 2022 39 commits
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Perry Yuan authored
Use ip versions (10,3,1) to match the GPU after Vangogh switched to use IP discovery path. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Perry Yuan <Perry.Yuan@amd.com> Signed-off-by:
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Perry Yuan authored
Add the missing apu flag for Vangogh when using IP discovery code path to initialize IPs Reviewed-by:
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Melissa Wen authored
DM maps DRM CRTC degamma to DPP (pre-blending) degamma block, but DCE doesn't support programmable degamma curve anywhere. Currently, a custom degamma is accepted by DM but just ignored by DCE driver and degamma correction isn't actually applied. There is no way to map custom degamma in DCE, therefore, DRM CRTC degamma property shouldn't be enabled for DCE drivers. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Aric Cyr authored
DC version 3.2.212 brings along the following fixes: - Fix DPIA AUX timeout issue - Add HUBP surface flip interrupt handler - Fix dpms_off issue when disabling bios mode - Update SubVP Visual Confirm - Program pipes for ODM when removing planes - Use min transition for all SubVP plane add/remove - Support parsing VRAM info v3.0 from VBIOS - Enable dchub request limit for NV32 - Workaround to increase phantom pipe vactive in pipesplit - Fix dcn3.1x mode validation on high bandwidth config - Check context constructed for pipe split flags after pipesplit - Align phantom pipe dst/src scaling with main for subvp - Fix calculation for cursor CAB allocation - Fix unbounded requesting for high pixel rate modes on dcn315 - Revert Disable DRR actions during state commit - Fix array index out of bound error in bios parser - Fix optc2_configure warning on dcn314 - Fix Subvp phantom pipe transition - Fix prefetch calculations for dcn32 - Use uclk pstate latency for fw assisted mclk validation dcn32 - Set max for prefetch lines on dcn32 - Rework macros for DWB register access - Adjust DP 8b10b LT exit behavior Reviewed-by:
Tom Chung <chiahsuan.chung@amd.com> Acked-by:
Aric Cyr <Aric.Cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
- New boot options to enable USB4 DP BW Allocation mode in DPIA Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Ilya Bakoulin authored
[Why] Polling SINK_STATUS DPCD can cause some non-DP2.0 LTTPR hubs to hang and no longer respond to AUX. [How] As a workaround for the problem hubs, and also to more closely match DP spec 8b10b behavior, don't poll for intra-hop AUX reply indication on 8b10b-encoded links. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why] A hack was used to access DWB register due to difference in the register naming convention which was not compatible with existing SR/SRI* macros. The additional macro needed were added to dwb ip specific header file (dcnxx_dwb.h) instead of soc resource file (dcnxx_resource.c). Due to this pattern, BASE macro had to be redefined in dcnxx_dwb.h, which in turn needed us to undefine them in the resource file. [How] Add a separate macro for DWB access to the resource files that need it instead of defining them in DWB ip header file. This will enable us to reuse the BASE macro defined in the resource file. Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Dillon Varone authored
[WHY?] Max number of lines that can be used for prefetch due to type constraints is 63.75. [HOW?] Enforce maximum prefetch lines as 63.75. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Dillon Varone <Dillon.Varone@amd.com> Tested-by:
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Dillon Varone authored
[WHY?] DCN32 uses fclk pstate watermarks for dummy pstate, and must always be supported. [HOW?] Validation needs to be run with fclk pstate latency set as the dummy pstate latency to get correct prefetch and bandwidth outputs. Reviewed-by:
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Dillon Varone authored
[Description] Prefetch calculation loop was not exiting until utilizing all of vstartup if it failed once. Locals need to be reset on each iteration of the loop. Reviewed-by:
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Alvin Lee authored
[Description] - When transitioning a pipe in use (non-phantom) to become a phantom pipe, we must fully disable the pipe first before doing any phantom pipe programming - Move phantom OTG enablement to after "regular" front-end programming sequence (including wait for vupdate) - If a pipe is being transitioned into a phantom pipe, fully disable it first Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Roman Li authored
[Why] dcn314 uses optc2_configure_crc() that wraps optc1_configure_crc() + set additional registers not applicable to dcn314. It's not critical but when used leads to warning like: WARNING: drivers/gpu/drm/amd/amdgpu/../display/dc/dc_helper.c Call Trace: <TASK> generic_reg_set_ex+0x6d/0xe0 [amdgpu] optc2_configure_crc+0x60/0x80 [amdgpu] dc_stream_configure_crc+0x129/0x150 [amdgpu] amdgpu_dm_crtc_configure_crc_source+0x5d/0xe0 [amdgpu] [How] Use optc1_configure_crc() directly Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why&How] Firmware headers dictate that gpio_pin array only has a size of 8. The count returned from vbios however is greater than 8. Fix this by not using array indexing but incrementing the pointer since gpio_pin definition in atomfirmware.h is hardcoded to size 8 Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Martin Leung authored
why and how: causes unstable on certain surface format/mpo transitions This reverts commit de020e5fReviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Alvin Lee authored
[Description] - If we're enabling phantom pipe for a high link rate display we could fail DML on the phantom pipe since it's set to virtual signal - Therefore don't consider Output BPP for phantom pipe Reviewed-by:
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Dmytro Laktyushkin authored
Unbounded requesting is getting configured for odm mode calculations which is incorrect. This change checks whether mode requires odm ahead of time. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by:
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George Shen authored
[Why] The cursor size (in memory) is currently incorrectly calculated, resulting not enough CAB being allocated for static screen cursor in MALL refresh. This results in cursor image corruption. [How] Use cursor pitch instead of cursor width when calculating cursor size. Update num cache lines calculation to use the result of the cursor size calculation instead of manually recalculating again. Reviewed-by:
George Shen <george.shen@amd.com> Tested-by:
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Dillon Varone authored
[WHY?] Subvp src/dst stream rectangles are not being created with the same scaling factors as the main stream. [HOW?] Make sure subvp stream src rectangle scales its height to have the same src/dst ratio as the main stream. Reviewed-by:
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Dillon Varone authored
[WHY?] After applying pipesplit flags, DML can select a different configuration upon revalidation, despite the desired one still being valid. [HOW?] Check the configuration is still has mode support, and apply it. Reviewed-by:
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Charlene Liu authored
[why] 1. correct dram_channel_width (was hard coded to 4 for 32bit) 2. use dm's is_hvm_enable status flag for hostvm_en input for dml. 3. add a function to override to all dcn3.1x. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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George Shen authored
[Why] Certain high resolution displays exhibit DCC line corruption with SubVP enabled. This is likely due to insufficient DCC meta data buffered immediately after the mclk switch. [How] Add workaround to increase phantom pipe vactive height by meta_row_height number of lines, thus increasing the amount of meta data buffered immediately after mclk switch finishes. Reviewed-by:
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Jun Lei authored
[why] HW recommend we enable this for better DF QoS for DCN 3.2.x [how] Add interfaces to hubbub to program register Add initialization as part of init_hw Add default settings for DCN 3.2.x Add registry override for debug/tuning Reviewed-by:
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George Shen authored
[Why] For DCN3.2 and DCN3.21, VBIOS has switch to using v3.0 of the VRAM info struct. We should read and override the VRAM info in driver with values provided by VBIOS to support memory downbin cases. Reviewed-by:
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Dmytro Laktyushkin authored
Stream only configurations do not require DCFCLK, SOCCLK, DPPCLK or FCLK. They also always allow pstate change. Reviewed-by:
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Alvin Lee authored
[Description] - Whenever disabling a phantom pipe, we must run through the minimal transition sequence - In the case where SetVisibility = false for the main pipe, we also need to run through the min transtion when disabling the phantom pipes Reviewed-by:
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Dillon Varone authored
[WHY?] Software state expects pipes to be configured for ODM, but due to the transition occurring on a plane disable, the ODM enablement code is not run. [HOW?] Update ODM when removing a plane, and dynamic ODM is active. Also acquire pipe lock when removing a plane. Reviewed-by:
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Liu Xi authored
[Why and how] Clean up some irq service code for dcn201. Reviewed-by:
Liu Xi <xi.liu@amd.com> Tested-by:
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David Galiffi authored
[Why] The visual confirm bar is displayed on all displays, but is only updated on a flip. If an update causes SubVP to be disabled on all displays, but there are no updates on the other displays, it will lead to stale information displayed on the non-active displays. An example of this is playing a fullscreen video on a rotated display. [How] Add a procedure to update visual confirm color for all pipes when committing a plane. Reviewed-by:
David Galiffi <David.Galiffi@amd.com> Tested-by:
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Zhongwei Zhang authored
[Why] disable_vbios_mode_if_required() will set dpms_off to false during boot when pixel clk dismatches with driver requires. This will cause extra backlight on and off if OS call 2 times setmode. [How] Set dpms_off to true to keep power_off and let OS control BL by display's powerState. Reviewed-by:
Zhongwei Zhang <Zhongwei.Zhang@amd.com> Tested-by:
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Stylon Wang authored
[Why] Some DPIA AUX replies have incorrect data length from original request. This could lead to overwriting of destination buffer if reply length is larger, which could cause invalid access to stack since many destination buffers are declared as local variables. [How] Check for invalid length from DPIA AUX replies and trigger a retry if reply length is not the same as original request. A DRM_WARN() dmesg log is also produced. Reviewed-by:
Stylon Wang <stylon.wang@amd.com> Tested-by:
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Candice Li authored
TA firmware loaded on psp v13_0_10, but it is missing in modinfo. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
On IGT, there is a test named amd_hotplug, and when the subtest basic is executed on DCN31, we get the following error: [drm] *ERROR* [CRTC:71:crtc-0] flip_done timed out [drm] *ERROR* flip_done timed out [drm] *ERROR* [CRTC:71:crtc-0] commit wait timed out [drm] *ERROR* flip_done timed out [drm] *ERROR* [CONNECTOR:88:DP-1] commit wait timed out [drm] *ERROR* flip_done timed out [drm] *ERROR* [PLANE:59:plane-3] commit wait timed out After enable the page flip log with the below command: echo -n 'format "[PFLIP]" +p' > /sys/kernel/debug/dynamic_debug/control It is possible to see that the flip was submitted, but DC never replied back, which generates time-out issues. This is an indication that the HUBP surface flip is missing. This commit fixes this issue by adding hubp1_set_flip_int to DCN31. Reviewed-by:
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Stylon Wang authored
[Why] Since introduction of patch "Query DPIA HPD status.", link detection at boot could be accessing DPIA AUX, which will not succeed until DMUB outbox messaging is enabled and results in below dmesg logs: [ 160.840227] [drm:amdgpu_dm_process_dmub_aux_transfer_sync [amdgpu]] *ERROR* wait_for_completion_timeout timeout! [How] Enable DMUB outbox messaging before link detection at boot time. Reviewed-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
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Alex Deucher authored
There are several places where we don't want to check if a particular asic could support DC, but rather, if DC is enabled. Set a flag if DC is enabled and check for that rather than if a device supports DC or not. Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Move it into the DCE code for each generation. This avoids confusion with the different display paths. v2: no need for a hotplug worker for vkms Acked-by:
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Alex Deucher authored
virtual display is enabled unconditionally in SR-IOV, but without specifying the virtual_display module, the number of crtcs defaults to 0. Set a single display by default for SR-IOV if the virtual_display parameter is not set. Only enable virtual display by default on SR-IOV on asics which actually have display hardware. Acked-by:
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Alex Deucher authored
amdgpu_device_asic_has_dc_support() just checks the asic itself. amdgpu_device_has_dc_support() is a runtime check which not only checks the asic, but also other things in the driver like whether virtual display is enabled. We want the latter here. Acked-by:
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Yifan Zha authored
[Why] GCMC_VM related registers should be programmed by PSP on host side. L1 and RLCG will block these regisers on VF. [How] Remove programming GCMC_VM_FB_LOCATION_BASE/TOP on gfxhub_v3_0_3 under SRIOV VF. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Reviewed-by:
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YuBiao Wang authored
Do not clear kiq position in RLC_CP_SCHEDULER so that CP could perform IDLE-SAVE after VF fini. CPG also needs to be active in save command. v2: drop unused variable (Alex) Signed-off-by:
YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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- 10 Nov, 2022 1 commit
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Dong Chenchen authored
When p->gang_size equals 0, amdgpu_cs_pass1() will return directly without freeing chunk_array, which will cause a memory leak issue, this patch fixes it. Fixes: 4624459c ("drm/amdgpu: add gang submit frontend v6") Reviewed-by:
Dong Chenchen <dongchenchen2@huawei.com> Signed-off-by:
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