- 06 Oct, 2022 40 commits
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Ruili Ji authored
This patch is to fix the SDMA user queue doorbell missing issue on SDMA 6.0. F32_WPTR_POLL_ENABLE has to be set if doorbell mode is used. Otherwise ringing SDMA user queue doorbell can't wake up system from gfxoff. Signed-off-by:
Ruili Ji <ruiliji2@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.0.x
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Yang Yingliang authored
In some error path in amdgpu_sdma_init_microcode(), release_firmware() is not called, the memory allocated in request_firmware() will be leaked, calling amdgpu_sdma_destroy_inst_ctx() which calls release_firmware() to avoid memory leak. Fixes: 15aa1305 ("drm/amdgpu: add function to init SDMA microcode") Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Signed-off-by:
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Yang Li authored
clean up one inconsistent indenting Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2321Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Yang Li authored
clean up one inconsistent indenting Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2238Reported-by:
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Rodrigo Siqueira authored
This commit adds some minor code style changes just to reduce the merge conflicts we have when we upstream some of the VBA code. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Update DSC checks in the DCN32 VBA. Reviewed-by:
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Rodrigo Siqueira authored
[Why] During transition from ODM combine to ODM bypass, if DSC is enabled need to disconnect the DSC mux for pipes no longer in use. [How] During ODM update, detect pipes with DSC that are no longer being used for new state and call new DSC interface to disconnect. Add new DSC interface to disconnect from pipe Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
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Martin Leung authored
why and how: needed to fix bad assumption for enable mcm_luts Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along the following: - ILR improvements - PSR fixes - DCN315 fixes - DCN32 fixes - ODM fixes - DSC fixes - SubVP fixes Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
If the current configuration supports 2 to 1 ODM policy, let's also enable the windowed MPO feature. Reviewed-by:
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Rodrigo Siqueira authored
For some reason, we missed the PState check for DCN32 which may cause issues for clock transition. This commit add that required hook. Reviewed-by:
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Sonny Jiang authored
Enable VCN PG on GC11_0_1 Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Wenjing Liu authored
There is a missing register mask in dcn32 causing the hardware programming is not executed when programming SQ_num test pattern for DP2. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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George Shen authored
[Why] Certain features require the additional DP SDP configuration registers DP_SEC_CNTL1 and DP_SEC_CNTL5 in order to function correctly. The DCN32 DIO stream encoder reglist is currently missing these two registers. [How] Add the missing registers to the DCN32 DIO stream encoder reglist. Reviewed-by:
George Shen <George.Shen@amd.com> Signed-off-by:
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Eric Bernstein authored
[Why] In DIO stream encoder, definition of DP_DSC_MODE is changed (only enable/disable) In OPTC, OTG_SET_V_TOTAL_MIN_MASK_EN is removed (same as DCN3.1) [How] In DIO stream encoder, update enc32_dp_set_dsc_config(). In OPTC, use DCN3.1 version for function interfaces .set_vrr_m_const and .set_drr Reviewed-by:
Eric Bernstein <eric.bernstein@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY&HOW?] When merging ODM pipes that are using MPO, we must copy the stream_res from the new top pipe to the bottom pipe so that the overlayed plane is not pointing to the wrong stream assets. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Dillon Varone <Dillon.Varone@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Add HDMI ACP bit field definition for DCN32. Reviewed-by:
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Rodrigo Siqueira authored
At some point, we decided to blank HUBP during pixel data blank, and to handle that, we added some OPTC lock checks. Later, we realized that this change caused multiple regression, and we removed it. Nevertheless, we still have some leftovers that might affect some ASIC behavior, and this commit drops those changes to keep the code consistent. Reviewed-by:
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Rodrigo Siqueira authored
SubVP has some issues related to how we allocate and enable it. This commit fixes this behavior by adding the proper check and configuration to the SubVP code path. Reviewed-by:
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Rodrigo Siqueira authored
DCN provides a hook to check if we can have a new pipe allocation based on some DC constraints. If the current configuration supports the new pipe request, DC updates its context; otherwise, it will keep the same configuration. This behavior is similar across multiple ASICs, and for this reason, we reused DCN20 on DCN321. However, this DCN32x has some peculiarities which require its function to avoid weird pipe split issues. This commit update this issue by using dcn32_acquire_idle_pipe_for_head_pipe_in_layer instead of dcn20_acquire_idle_pipe_for_layer. Reviewed-by:
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Rodrigo Siqueira authored
Under DCN32/321 we identified some code paths that DC never executes. This commit removes those unused codes to avoid distractions when debugging issues. Reviewed-by:
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Martin Leung authored
why: when dynamic odm was turned on, there is also logic to halve the pixelclk this still turned on when we avoided odm in the case of odd h_total timings how: block the pixel clk mechanism also in the case of odd h_total timings Reviewed-by:
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Aric Cyr authored
[how] Large deltas for periodic interrupts could result in the interrupt not being programmed properly and thus not firing. [why] Add proper wrap-around support for calculating VUPDATE and VLINE positions. Reviewed-by:
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Wenjing Liu authored
[why] According to specs, it expects us to write all 4 bytes even if current lane count is less than 4. Reviewed-by:
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Dillon Varone authored
[WHY?] Clocks are updating based on the incoming context's support, however the new compbuf size is not programmed prior to udpating clocks, which can result in P-State hangs. [HOW?] Increase compbuf size prior to updating clocks. Reviewed-by:
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Lewis Huang authored
[Why] Disable OTG when PSRSU with z10 even if z10 is disable [How] Reverse condition to keep OTG on when Z10 is disable Reviewed-by:
Robin Chen <po-tchen@amd.com> Acked-by:
Lewis Huang <Lewis.Huang@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
DCN315 has to always allow pstate change or SMU will hang. This workaround achieves this by applying a low pstate change latency to be used when pstate is calculated to be unsupported. This lower latency only accounts for memory retraining; a previous change handles locking in the highest available pstate allowing us to minimize required latency hiding to only account for memory retraining. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Zhikai Zhai authored
[WHY] Now dynamic ODM will now be disabled when MPO is required safe transitions to avoid underflow, but we are triggering the way of minimal transition too often. Commit state of dc with no check will do pipeline setup which may re-initialize the component with no need such as audio. [HOW] Just do the minimal transition when all of pipes are in use, otherwise return true to skip. Reviewed-by:
Zhikai Zhai <zhikai.zhai@amd.com> Signed-off-by:
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Leo Chen authored
[Why & How] Adding log for LTTPR to facilitate debugging. Reviewed-by:
Leo Chen <sancchen@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] - For SubVP pipe split case we need to use a minimial transition when opening MPO video since we are transitioning from 4 pipes to 3 pipes where an OPP for a previous MPCC will change - Also save and restore mall config when doing fast_validate in case there was a shallow copy of the dc->current_state Reviewed-by:
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Ian Chen authored
We split out ILR config from "global" to "per-panel" config settings. Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Ian Chen <ian.chen@amd.com> Signed-off-by:
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Iswara Nagulendran authored
[HOW&WHY] Fixed check to only avoid PSR entry when panel is disconnected. PSR exit can be permitted to restore the HW to it's non-PSR state. Reviewed-by:
Jayendran Ramani <Jayendran.Ramani@amd.com> Acked-by:
Iswara Nagulendran <Iswara.Nagulendran@amd.com> Signed-off-by:
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Leo (Hanghong) Ma authored
[Why && How] Remove the unnecessary AUX trace and use one trace for AUX failure. Reviewed-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] Analyzer shows incorrect V freq in MSA for some large timing. [how] Cast an 32 bit integer to uint64_t before multiplication to avoid integer overflow for a very large timing. Reviewed-by:
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Alvin Lee authored
[Description] When enabling phantom pipe on a pipe that was previously using immediate flip, we have to disable GSL or this will prevent the update from taking place right away on the phantom pipe when we enable it in FW Reviewed-by:
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Charlene Liu authored
[why] limit the vm prefetch check for now, until the feature is fully verified. Reviewed-by:
Hansen Dsouza <Hansen.Dsouza@amd.com> Acked-by:
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Aric Cyr authored
This reverts commit 796d6a37. 4K144 resolution isn't available on DCN31. Reviewed-by:
Sherry Wang <Yao.Wang1@amd.com> Acked-by:
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Alvin Lee authored
[Description] - SubVP rotation support is not explicitly implemented, so block SubVP in rotation cases to avoid unexpected behaviors Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
DML does not take the fact that dcn315 does not have enough detile buffer to max all pipes. This change adds a workaround to apply the same logic DC does when calculating detile buffer size in DML. Reviewed-by:
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Dillon Varone authored
[WHY?] In some cases, DCFCLK hardmin requests are not acknowledged by SMU as the requested clock does not have a compatible ratio with current FCLK, and it cannot be changed as FCLK P-state is not allowed. [HOW?] Allow FCLK p-state change prior to changing DCFCLK hardmin. Reviewed-by:
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