- 19 Oct, 2021 21 commits
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Eric Yang authored
[Why] Z9 latency is higher than when we originally tuned the watermark parameters, causing underflow. Increasing the value until the latency issues is resolved. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com> Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicholas Kazlauskas authored
[Why] Immediate flip can be enabled dynamically and has higher BW requirements when validating which voltage mode to use. If we validate when it's not set then potentially DCFCLK will be too low and we will underflow. [How] DM always requires support so always require it as part of DML input parameters. This can't be enabled unconditionally on older ASIC because it blocks some expected modes so only target DCN3.1 for now. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Jake Wang authored
[Why & How] Disable root clock for dsc when not being used. Reviewed-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
Jake Wang <haonan.wang2@amd.com> Tested-by:
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Mikita Lipski authored
[why] PSR_STATE2b was introduced on DMCUB side, but not on the driver side, which caused convert_psr_state helper function to return PSR_STATE_INVALID. That caused visual lagging during state transition. [how] Add PSR_STATE2b to dc_psr_state and convert_psr_state Reviewed-by:
Wyatt Wood <Wyatt.Wood@amd.com> Acked-by:
Mikita Lipski <mikita.lipski@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] Prefetch BW calculated is lower than the DML reference because of a porting error that's excluding cursor and row bandwidth from the pixel data bandwidth. [How] Change the dml_max4 to dml_max3 and include cursor and row bandwidth in the same calculation as the rest of the pixel data during vactive. Reviewed-by:
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Hansen authored
Remap phyd32clk to PHYF and PHYG for B0, PHYC and PHYD are unused Reviewed-by:
Hansen <Hansen.Dsouza@amd.com> Tested-by:
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Nikola Cornij authored
[why] The requirement is that image width up to 4096 shall be supported Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Lai, Derek authored
[Why] Error message on Linux when booting. [How] Removed power down on boot from DCN31 HW init to match DCN10 HW init. Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Derek Lai <derek.lai@amd.com> Tested-by:
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Aric Cyr authored
[Why] Calculation of scaling ratio can result in a crash due to zero'd src or dst plane rects. [How] Validate that src and dst rects are valid before using for scaling calculations. Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Acked-by:
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Wenjing Liu authored
Hardware team has recommended to generically hard code this register to 0xFF as part of the effort to eventually remove this control. However we set it to 0xF instead. This causes 4 of audio 8ch to be muted. Reviewed-by:
Ariel Bernstein <eric.bernstein@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Josip Pavic authored
[Why & How] Increase width of some variables to avoid comparing integers of different widths Reviewed-by:
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Michael Strauss authored
[WHAT] One of the current VPG power on calls is unnecessary Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Wenjing Liu authored
[why] Some DP2.0 RX requires us to set MST_EN even for SST configuration. We added this debug option so we can configure this temporary workaround for the RX. Reviewed-by:
George Shen <george.shen@amd.com> Acked-by:
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Jimmy Kizito authored
[Why] When rapidly plugging and unplugging a DP sink, detection link training can be mistakenly skipped. This is due to the hotplug processing occurring before the encoder assignment logic has had a chance to process the removal of a stream. The encoder that would be used for detection link training is then erroneously reported as already in use and detection link training is skipped. [How] During hot plug processing, only determine a link encoder to be unavailable for a particular link if it has been assigned to a different link. Reviewed-by:
Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by:
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Jimmy Kizito authored
[Why] When copying a stream, the encoder assigned to it is copied too. Encoder assignment should only happen when executing the encoder assignment function link_encs_assign(). [How] Clear the link encoder pointer for copied stream. Reviewed-by:
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Jake Wang authored
[Why & How] Disable root clock for dpp when not being used. Reviewed-by:
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Roman Li authored
[Why] On renoir usb-c port stops functioning on resume after f/w update. New dmub firmware caused regression due to conflict with dmcu. With new dmub f/w dmcu is superseded and should be disabled. [How] - Disable dmcu for all dcn21. Check dmesg for dmub f/w version. The old firmware (before regression): [drm] DMUB hardware initialized: version=0x00000001 All other versions require this patch for renoir. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1735Acked-by:
Harry Wentland <harry.wentland@amd.com> Tested-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
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YuBiao Wang authored
[Why] drm_irq_uninstall is called in irq_fini_hw so that irq is disabled in sw stage. SMU (and maybe other IP blocks) fini_hw will call irq_put for cleanup and the whole cleanup process will be skipped because of drm->irq_enable = false. [How] Move ip_fini_early before irq_fini_hw. Signed-off-by:
YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Jonathan Kim authored
ROCr needs to be able to identify all devices that have direct access to fine grain memory, which should include CPUs that are connected to GPUs over xGMI. The GPU hive ID can be mapped onto the CPU hive ID since the CPU is part of the hive. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Tao Zhou authored
Some registers' access will fail without PSP RL after resume. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Lang Yu authored
We should unreference a gem object instead of an amdgpu bo here. Fixes: fd9a9f88 ("drm/amdgpu: Use GEM obj reference for KFD BOs") Signed-off-by:
Lang Yu <lang.yu@amd.com> Reviewed-by:
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- 14 Oct, 2021 4 commits
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Alex Deucher authored
Missed a few asics. v2: update comment Fixes: 82d05736 ("drm/amdgpu/amdgpu_psp: convert to IP version checking") Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
VEGA20 is 11.0.2, but it's handled by powerplay, not swsmu. Fixes: a8967967 ("drm/amdgpu/amdgpu_smu: convert to IP version checking") Reviewed-by:
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Philip Yang authored
When creating unregistered new svm range to recover retry fault, avoid new svm range to overlap with ranges or userptr ranges managed by TTM, otherwise svm migration will trigger TTM or userptr eviction, to evict user queues unexpectedly. Change helper amdgpu_ttm_tt_affect_userptr to return userptr which is inside the range. Add helper svm_range_check_vm_userptr to scan all userptr of the vm, and return overlap userptr bo start, last. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Thelford Williams authored
Size can be any value and is user controlled resulting in overwriting the 40 byte array wr_buf with an arbitrary length of data from buf. Signed-off-by:
Thelford Williams <tdwilliamsiv@gmail.com> Signed-off-by:
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- 13 Oct, 2021 15 commits
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Alex Deucher authored
Was missed in the conversion to IP version checking. Fixes: af3b89d3 ("drm/amdgpu/smu11.0: convert to IP version checking") Reviewed-by:
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Harry Wentland authored
He's been helping maintain it for quite a while now. Make it official. Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Yifan Zhang authored
When IOMMU disabled in sbios and kfd in iommuv2 path, IOMMU resume failure blocks system resume. Don't allow kfd to use iommu v2 when iommu is disabled. Reported-by:
youling <youling257@gmail.com> Tested-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Yifan Zhang authored
When IOMMU disabled in sbios and kfd in iommuv2 path, iommuv2 init will fail. But this failure should not block amdgpu driver init. Reported-by:
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Philip Yang authored
migrate_vma_setup may return cpages 0, means 0 page can be migrated, treat this as error case to skip the rest of vma migration steps. Change svm_migrate_vma_to_vram and svm_migrate_vma_to_ram to return the number of pages migrated successfully or error code. The caller add up all the successful migration pages and update prange->actual_loc only if the total migrated pages is not 0. This also removes the warning message "VRAM BO missing during validation" if migration cpages is 0. Signed-off-by:
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Philip Yang authored
No function change, use pr_debug_ratelimited to avoid per page debug message overflowing dmesg buf and console log. use dev_err to show error message from unexpected situation, to provide clue to help debug without enabling dynamic debug log. Define dev_fmt to output function name in error message. Signed-off-by:
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Darren Powell authored
when smu->adev->pm.ac_power == 0, message parameter with bit 16 set is saved to smu->current_power_limit. Fixes: 0cb4c621 ("drm/amd/pm: correct power limit setting for SMU V11)" Signed-off-by:
Darren Powell <darren.powell@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Darren Powell authored
v2 add check for SMU_DEFAULT_PPT_LIMIT v1 modify (pptable_funcs)->set_power_limit signature modify smu11 set_power_limit signature (arcturus, navi10, sienna_cichlid) modify smu13 set_power_limit signature (aldabaran) modify vangogh_set_power_limit signature (vangogh) === Test === sudo bash AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} LOGFILE=pp_show_power_cap.log cp $LOGFILE{,.old} lspci -nn | grep "VGA\|Display" > $LOGFILE FILES=" power1_cap power2_cap" for f in $FILES do if test -f "$HWMON_DIR/$f"; then echo === $f === >> $LOGFILE cat $HWMON_DIR/$f >> $LOGFILE RESTORE_VALUE=`cat $HWMON_DIR/$f` 2>&1 >> $LOGFILE echo RESTORE_VALUE $RESTORE_VALUE >> $LOGFILE echo 120000000 > $HWMON_DIR/$f sleep 3 cat $HWMON_DIR/$f >> $LOGFILE echo $RESTORE_VALUE > $HWMON_DIR/$f sleep 3 cat $HWMON_DIR/$f >> $LOGFILE else echo === $f === >> $LOGFILE echo File Not Found >> $LOGFILE fi done cat $LOGFILE Signed-off-by: -
Mukul Joshi authored
During mode2 reset, the GPU is temporarily removed from the mgpu_info list. As a result, page retirement fails because it cannot find the GPU in the GPU list. To fix this, create our own list of GPUs that support MCE notifier based page retirement and use that list to check if the UMC error occurred on a GPU that supports MCE notifier based page retirement. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
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Mukul Joshi authored
Add the missing call to re-enable RAS error injections on the Aldebaran mode2 reset code path. Signed-off-by:
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Aurabindo Pillai authored
[Why&How] When system boots in headless mode, connecting a 4k display creates a null pointer dereference due to hubp for a certain plane being null. Add a condition to check for null hubp before dereferencing it. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] DCE legacy optimization path isn't well tested under new DC optimization flow which can result in underflow occuring when initializing X11 on Carrizo. [How] Retain the legacy optimization flow for DCE and keep the new one for DCN to satisfy optimizations being correctly applied for ASIC that can support it. Fixes: 34316c1e ("drm/amd/display: Optimize bandwidth on following fast update") Reported-by:
Tom St Denis <tom.stdenis@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] For optimal power savings on panels that can support it. This was previously left disabled by default because of issues with compositors that do not pageflip and scan out directly to the frontbuffer. For these compositors we now have detection methods that wait for x number of pageflips after a full update - triggered by a buffer or format change typically. This may introduce bugs or new cases not tested by users so this is only currently targeting newer DCN. [How] Add code in DM to set PSR state by default for newer DCN while falling back to the feature mask for older. Add a global debug flag that can be set to disable it for either. Signed-off-by:
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Lang Yu authored
Display support for cyan skillfish is ready now. Enable it! Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Simon Ser authored
The current logic checks whether the cursor plane blending properties match the primary plane's. However that's wrong, because the cursor is painted on all planes underneath. If the cursor is over the primary plane and the overlay plane, it's painted on both pipes. Iterate over the CRTC planes and check their scaling match the cursor's. v4: fix typo in commit message (Harry) Signed-off-by:
Simon Ser <contact@emersion.fr> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Sean Paul <seanpaul@chromium.org> Reviewed-by:
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