1. 09 Nov, 2017 2 commits
    • James Hogan's avatar
      MIPS: Fix MIPS64 FP save/restore on 32-bit kernels · 22b8ba76
      James Hogan authored
      32-bit kernels can be configured to support MIPS64, in which case
      neither CONFIG_64BIT or CONFIG_CPU_MIPS32_R* will be set. This causes
      the CP0_Status.FR checks at the point of floating point register save
      and restore to be compiled out, which results in odd FP registers not
      being saved or restored to the task or signal context even when
      CP0_Status.FR is set.
      
      Fix the ifdefs to use CONFIG_CPU_MIPSR2 and CONFIG_CPU_MIPSR6, which are
      enabled for the relevant revisions of either MIPS32 or MIPS64, along
      with some other CPUs such as Octeon (r2), Loongson1 (r2), XLP (r2),
      Loongson 3A R2.
      
      The suspect code originates from commit 597ce172 ("MIPS: Support for
      64-bit FP with O32 binaries") in v3.14, however the code in
      __enable_fpu() was consistent and refused to set FR=1, falling back to
      software FPU emulation. This was suboptimal but should be functionally
      correct.
      
      Commit fcc53b5f ("MIPS: fpu.h: Allow 64-bit FPU on a 64-bit MIPS R6
      CPU") in v4.2 (and stable tagged back to 4.0) later introduced the bug
      by updating __enable_fpu() to set FR=1 but failing to update the other
      similar ifdefs to enable FR=1 state handling.
      
      Fixes: fcc53b5f ("MIPS: fpu.h: Allow 64-bit FPU on a 64-bit MIPS R6 CPU")
      Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org> # 4.0+
      Patchwork: https://patchwork.linux-mips.org/patch/16739/
      22b8ba76
    • Florian Fainelli's avatar
      MIPS: page.h: Define virt_to_pfn() · 37d15948
      Florian Fainelli authored
      Define virt_to_pfn() based on the existing definition of virt_to_page()
      which already does a PFN_DOWN(vir_to_phys(kaddr)).
      Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paul Burton <paul.burton@mips.com>
      Cc: Maciej W. Rozycki <macro@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/15409/Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
      37d15948
  2. 08 Nov, 2017 8 commits
  3. 07 Nov, 2017 16 commits
  4. 09 Oct, 2017 8 commits
  5. 07 Oct, 2017 4 commits
  6. 06 Oct, 2017 2 commits
    • Linus Torvalds's avatar
      Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux · dbeb1a8f
      Linus Torvalds authored
      Pull clk fixes from Stephen Boyd:
      
       - build fix to export the clk_bulk_prepare() symbol
      
       - suspend fix for Samsung Exynos SoCs where we need to keep clks on
         across suspend
      
       - two critical clk markings for clks that shouldn't ever turn off on
         Rockchip SoCs
      
       - a fix for a copy-paste mistake on Rockchip rk3128 causing some clks
         to touch the same bit and trample over one another
      
      * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
        clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle
        clk: Export clk_bulk_prepare()
        clk: rockchip: add sclk_timer5 as critical clock on rk3128
        clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs error
        clk: rockchip: add pclk_pmu as critical clock on rk3128
      dbeb1a8f
    • Linus Torvalds's avatar
      Merge tag 'arc-4.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc · ed0f72f4
      Linus Torvalds authored
      Pull ARC udpates from Vineet Gupta:
      
       - updates for various platforms
      
       - boot log updates for upcoming HS48 family of cores (dual issue)
      
      * tag 'arc-4.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
        ARC: [plat-hsdk]: Add reset controller node to manage ethernet reset
        ARC: [plat-hsdk]: Temporary fix to set CPU frequency to 1GHz
        ARC: fix allnoconfig build warning
        ARCv2: boot log: identify HS48 cores (dual issue)
        ARC: boot log: decontaminate ARCv2 ISA_CONFIG register
        arc: remove redundant UTS_MACHINE define in arch/arc/Makefile
        ARC: [plat-eznps] Update platform maintainer as Noam left
        ARC: [plat-hsdk] use actual clk driver to manage cpu clk
        ARC: [*defconfig] Reenable soft lock-up detector
        ARC: [plat-axs10x] sdio: Temporary fix of sdio ciu frequency
        ARC: [plat-hsdk] sdio: Temporary fix of sdio ciu frequency
        ARC: [plat-axs103] Add temporary quirk to reset ethernet IP
      ed0f72f4