- 14 Mar, 2011 10 commits
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Dave Airlie authored
* 'nouveau/drm-nouveau-next' of ../drm-nouveau-next: drm/nouveau: fix __nouveau_fence_wait performance drm/nv40: attempt to reserve just enough vram for all 32 channels drm/nv50: check for vm traps on every gr irq drm/nv50: decode vm faults some more drm/nouveau: add nouveau_enum_find() util function drm/nouveau: properly handle pushbuffer check failures drm/nvc0: remove vm hack forcing large/small pages to not share a PDE
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Marcin Slusarz authored
Commit 21e86c1c ("drm/nouveau: remove cpu_writers lock") turned on lazy waits. Unfortunately __nouveau_fence_wait was not optimized for this case and on HZ=100 kernel wasted up to 10 ms per call. Depending on application, it led to 10-30% FPS regression. Fix it. Signed-off-by:
Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by:
Francisco Jerez <currojerez@riseup.net>
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Ben Skeggs authored
This also makes the fact we're giving 512MiB of GART space to all PCIE boards explicit, although the vast majority (if not all) of them will now have a ramin_rsvd_vram larger than 2MiB anyway. Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Marcin Slusarz authored
When "buffer in list" check does not pass, don't free validation lists - they were not initialized yet. Fixes this oops: [drm] nouveau 0000:02:00.0: push 105 buffer not in list BUG: unable to handle kernel NULL pointer dereference at 000000000000057c IP: [<ffffffff81236aa4>] do_raw_spin_lock+0x14/0x13c PGD 1ac6cb067 PUD 1aaa52067 PMD 0 CPU 0 Modules linked in: nouveau ttm drm_kms_helper snd_hda_codec_realtek snd_hda_intel snd_hda_codec Pid: 6265, comm: OilRush_x86 Not tainted 2.6.38-rc6-nv+ #632 System manufacturer System Product Name/P6T SE RIP: 0010:[<ffffffff81236aa4>] [<ffffffff81236aa4>] do_raw_spin_lock+0x14/0x13c (...) Process OilRush_x86 (pid: 6265, threadinfo ffff8801a6aee000, task ffff8801a26c0000) 0000000000000000 ffff8801ac74c618 0000000000000000 0000000000000578 0000000000000000 ffff8801ac74c618 0000000000000000 ffff8801bd9d0000 [<ffffffff81417f78>] _raw_spin_lock+0x1e/0x22 [<ffffffffa00a2746>] nouveau_bo_fence+0x2e/0x60 [nouveau] [<ffffffffa00a540b>] validate_fini_list+0x35/0xeb [nouveau] [<ffffffffa00a54d3>] validate_fini+0x12/0x31 [nouveau] [<ffffffffa00a6386>] nouveau_gem_ioctl_pushbuf+0xe94/0xf6b [nouveau] [<ffffffff8141ac56>] ? sub_preempt_count+0x9e/0xb2 [<ffffffff81417e94>] ? _raw_spin_unlock_irqrestore+0x30/0x4d [<ffffffff8105dea2>] ? __wake_up+0x3f/0x48 [<ffffffff812aebb4>] drm_ioctl+0x289/0x361 [<ffffffff8141ac56>] ? sub_preempt_count+0x9e/0xb2 [<ffffffffa00a54f2>] ? nouveau_gem_ioctl_pushbuf+0x0/0xf6b [nouveau] [<ffffffff8141ac56>] ? sub_preempt_count+0x9e/0xb2 [<ffffffffa010caa2>] nouveau_compat_ioctl+0x16/0x1c [nouveau] [<ffffffff81142c0d>] compat_sys_ioctl+0x1c8/0x12d7 [<ffffffff814179ca>] ? trace_hardirqs_off_thunk+0x3a/0x6c [<ffffffff81058099>] sysenter_dispatch+0x7/0x30 [<ffffffff8141798e>] ? trace_hardirqs_on_thunk+0x3a/0x3c RIP [<ffffffff81236aa4>] do_raw_spin_lock+0x14/0x13c RSP <ffff8801a6aefb88> ---[ end trace 0014d5d93e6147e1 ]--- Additionally, don't call validate_fini twice in case of validation failure. Signed-off-by:
Maarten Maathuis <madman2003@gmail.com> Signed-off-by:
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Ben Skeggs authored
Appears to be fixed with commit: "drm/nv50-nvc0: make sure vma is definitely unmapped when destroying bo" Signed-off-by: -
Dave Airlie authored
At least on my HP 2540p this is wrong at bootup, fine at any other time once a lid event has occured. This is due to _REG vs _INI ordering in the ACPI tables. Signed-off-by:Dave Airlie <airlied@redhat.com>
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Dave Airlie authored
* 'intel/drm-intel-next' of ../drm-next: (755 commits) drm/i915: Only wait on a pending flip if we intend to write to the buffer drm/i915/dp: Sanity check eDP existence drm/i915: Rebind the buffer if its alignment constraints changes with tiling drm/i915: Disable GPU semaphores by default drm/i915: Do not overflow the MMADDR write FIFO Revert "drm/i915: fix corruptions on i8xx due to relaxed fencing" drm/i915: Don't save/restore hardware status page address register drm/i915: don't store the reg value for HWS_PGA drm/i915: fix memory corruption with GM965 and >4GB RAM Linux 2.6.38-rc7 Revert "TPM: Long default timeout fix" drm/i915: Re-enable GPU semaphores for SandyBridge mobile drm/i915: Replace vblank PM QoS with "Interrupt-Based AGPBUSY#" Revert "drm/i915: Use PM QoS to prevent C-State starvation of gen3 GPU" drm/i915: Allow relocation deltas outside of target bo drm/i915: Silence an innocuous compiler warning for an unused variable fs/block_dev.c: fix new kernel-doc warning ACPI: Fix build for CONFIG_NET unset mm: <asm-generic/pgtable.h> must include <linux/mm_types.h> x86: Use u32 instead of long to set reset vector back to 0 ... Conflicts: drivers/gpu/drm/i915/i915_gem.c
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- 07 Mar, 2011 5 commits
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Chris Wilson authored
Apply the trivial conflicting regression fixes, but keep GPU semaphores enabled. Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_gem_execbuffer.c
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Chris Wilson authored
... as if we are only reading from it, we can do that concurrently with the queue flip. Signed-off-by:Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Some hardware claims to have both an LVDS panel and an eDP output. Whilst this may be true in a rare case, more often it is just broken hardware. If we see an eDP device we know that it must be connected and so we can confirm its existence with a simple probe. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34165 Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=24822Signed-off-by:
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Chris Wilson authored
Early gen3 and gen2 chipset do not have the relaxed per-surface tiling constraints of the later chipsets, so we need to check that the GTT alignment is correct for the new tiling. If it is not, we need to rebind. Reported-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by:
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Chris Wilson authored
Andi Kleen narrowed his GPU hangs on his Sugar Bay (SNB desktop) rev 09 down to the use of GPU semaphores, and we already know that they appear broken up to Huron River (mobile) rev 08. (I'm optimistic that disabling GPU semaphores is simply hiding another bug by the latency and side-effects of the additional device interaction it introduces...) However, use of semaphores is a massive performance improvement... Only as long as the system remains stable. Enable at your peril. Reported-by:
Andi Kleen <andi-fd@firstfloor.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33921Signed-off-by:
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- 06 Mar, 2011 2 commits
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Chris Wilson authored
Whilst the GT is powered down (rc6), writes to MMADDR are placed in a FIFO by the System Agent. This is a limited resource, only 64 entries, of which 20 are reserved for Display and PCH writes, and so we must take care not to queue up too many writes. To avoid this, there is counter which we can poll to ensure there are sufficient free entries in the fifo. "Issuing a write to a full FIFO is not supported; at worst it could result in corruption or a system hang." Reported-and-Tested-by:
Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34056Signed-off-by:
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Chris Wilson authored
This reverts commit c2e0eb16. As it turns out, userspace already depends upon being able to enable tiling on existing bo which it promises to be large enough for its purposes i.e. it will not access beyond the end of the last full-tile row. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35016Reported-and-tested-by:
Kamal Mostafa <kamal@canonical.com> Signed-off-by:
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- 04 Mar, 2011 2 commits
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Dave Airlie authored
This allows libkms to make an easier decision. Signed-off-by: -
Ben Skeggs authored
We're coming to see a need to have a set of generic capability checks in the core DRM, in addition to the driver-specific ioctls that already exist. This patch defines an ioctl to do as such, but does not yet define any capabilities. [airlied: drop the driver callback for now.] Signed-off-by:
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- 03 Mar, 2011 17 commits
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Alex Deucher authored
hdmi 1.3 raises the max clock from 165 Mhz to 340 Mhz. Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
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Dave Airlie authored
* korg/drm-radeon-cayman: drm/radeon/kms: add cayman pci ids drm/radeon/kms: cayman/evergreen cs checker updates drm/radeon/kms/cayman: always set certain VGT regs at CP init drm/radeon/kms: additional default context regs for cayman drm/radeon/kms: add cayman CS check support drm/radeon/kms: add radeon_asic entry for cayman drm/radeon/kms: add cayman safe regs drm/radeon/kms/cayman: add asic init/startup/fini/suspend/resume functions drm/radeon/kms: add cayman asic reset support drm/radeon/kms: add support for cayman irqs drm/radeon/kms: add support for CP setup on cayman asics drm/radeon/kms: add support for cayman gart setup drm/radeon/kms: add gpu_init function for cayman drm/radeon/kms: add ucode loader for cayman drm/radeon/kms: add cayman chip family
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
These should be handled by the clear_state setup, but set them directly as well just to be sure. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
Added to existing evergreen CS checker. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
For the CS checker. Signed-off-by:
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Alex Deucher authored
Cayman is different enough from evergreen to warrant it's own functions. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
Cayman asics have 3 ring buffers: ring 0 supports both gfx and compute rings 1 and 2 are compute only At the moment we only support ring 0. Signed-off-by:
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Alex Deucher authored
This patch sets up the gart in legacy mode. We probably want to switch to full VM mode at some point. Signed-off-by:
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Alex Deucher authored
This may some work to get accel going. Signed-off-by:
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Alex Deucher authored
The MC ucode is no longer loaded by the vbios tables as on previous asics. It now must be loaded by the driver. Signed-off-by:
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Alex Deucher authored
Cayman is DCE5 display plus a new 4-way shader block. 3D state programming is similar to evergreen. Signed-off-by:
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- 02 Mar, 2011 2 commits
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Zhenyu Wang authored
It's cleaned before saving and re-initialized after restoring. So don't need to save/restore it. And also new chip has new address for hardware status page register, don't write to old address. Signed-off-by:
Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by:
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Chris Wilson authored
It is trivially computable from the real physical address so no need to store both. Signed-off-by:
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- 01 Mar, 2011 2 commits
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Chris Wilson authored
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Jan Niehusmann authored
On a Thinkpad x61s, I noticed some memory corruption when plugging/unplugging the external VGA connection. The symptoms are that 4 bytes at the beginning of a page get overwritten by zeroes. The address of the corruption varies when rebooting the machine, but stays constant while it's running (so it's possible to repeatedly write some data and then corrupt it again by plugging the cable). Further investigation revealed that the corrupted address is (dev_priv->status_page_dmah->busaddr & 0xffffffff), ie. the beginning of the hardware status page of the i965 graphics card, cut to 32 bits. So it seems that for some memory access, the hardware uses only 32 bit addressing. If the hardware status page is located >4GB, this corrupts unrelated memory. Signed-off-by:
Jan Niehusmann <jan@gondor.com> Acked-by:
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