- 21 Dec, 2020 1 commit
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Stephen Boyd authored
Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', 'clk-renesas' and 'clk-samsung' into clk-next - Camera clks on Qualcomm SC7180 SoCs - GCC and RPMh clks on Qualcomm SDX55 SoCs - RPMh clks on Qualcomm SM8350 SoCs - LPASS clks on Qualcomm SM8250 SoCs - Add devm variant of clk_notifier_register() - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw * clk-doc: clk: fix a kernel-doc markup * clk-qcom: (27 commits) clk: qcom: rpmh: add support for SM8350 rpmh clocks dt-bindings: clock: Add RPMHCC bindings for SM8350 clk: qcom: lpasscc: Introduce pm autosuspend for SC7180 clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2 clk: qcom: gcc-sc7180: Use floor ops for sdcc clks clk: qcom: Add GDSC support for SDX55 GCC dt-bindings: clock: Add GDSC in SDX55 GCC clk: qcom: Add support for SDX55 RPMh clocks dt-bindings: clock: Introduce RPMHCC bindings for SDX55 clk: qcom: Add SDX55 GCC support dt-bindings: clock: Add SDX55 GCC clock bindings clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic" clk: qcom: rpmh: Add CE clock on sdm845. dt-bindings: clock: Add entry for crypto engine RPMH clock resource clk: qcom: dispcc-sm8250: handle MMCX power domain clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init() clk: qcom: Add support to LPASS AON_CC Glitch Free Mux clocks clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks dt-bindings: clock: Add support for LPASS Always ON Controller ... * clk-simplify: clk: remove unneeded dead-store initialization * clk-hw: clk: meson: g12: use devm variant to register notifiers clk: add devm variant of clk_notifier_register clk: meson: g12: drop use of __clk_lookup() clk: add api to get clk consumer from clk_hw clk: avoid devm_clk_release name clash * clk-renesas: dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema clk: renesas: sh73a0: Stop using __raw_*() I/O accessors clk: renesas: r8a774c0: Add RPC clocks clk: renesas: r8a779a0: Fix R and OSC clocks clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get() clk: renesas: r8a774b1: Add RPC clocks clk: renesas: r8a774a1: Add RPC clocks clk: renesas: r8a779a0: Add VIN clocks clk: renesas: r8a779a0: Add CSI4[0-3] clocks MAINTAINERS: Update git repo for Renesas clock drivers clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI * clk-samsung: clk: samsung: Prevent potential endless loop in the PLL ops clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
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- 10 Dec, 2020 18 commits
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Stephen Boyd authored
Merge tag 'renesas-clk-for-v5.11-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Update git repo branch for Renesas clock drivers - Add camera (CSI) and video-in (VIN) clocks on R-Car V3U - Add RPC (QSPI/HyperFLASH) clocks on RZ/G2M, RZ/G2N, and RZ/G2E - Stop using __raw_*() I/O accessors - One more conversion of DT bindings to json-schema - Minor fixes and improvements * tag 'renesas-clk-for-v5.11-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema clk: renesas: sh73a0: Stop using __raw_*() I/O accessors clk: renesas: r8a774c0: Add RPC clocks clk: renesas: r8a779a0: Fix R and OSC clocks clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get() clk: renesas: r8a774b1: Add RPC clocks clk: renesas: r8a774a1: Add RPC clocks clk: renesas: r8a779a0: Add VIN clocks clk: renesas: r8a779a0: Add CSI4[0-3] clocks MAINTAINERS: Update git repo for Renesas clock drivers clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI
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Vinod Koul authored
This adds the RPMH clocks present in SM8350 SoC Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20201208064702.3654324-3-vkoul@kernel.org [sboyd@kernel.org: Move sdx55 to the right place] Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Vinod Koul authored
Add bindings and update documentation for clock rpmh driver on SM8350. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Taniya Das authored
The LPASSCC driver's suspend/resume is invoked multiple number of times and thus allow the device to autosuspend for 500ms. Signed-off-by:
Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1605890417-721-1-git-send-email-tdas@codeaurora.orgSigned-off-by:
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Douglas Anderson authored
50 MHz is an incredibly common clock rate for SD cards to run at. It's "high speed" mode in SD (not very fast these days, but it used to be) or: #define HIGH_SPEED_MAX_DTR 50000000 If we don't support this then older "high speed" cards can only run at 25 MHz or at half their normal speed. There doesn't seem to be any reason to skip this clock rate, so add it. Fixes: 17269568 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20201210102234.2.I26dcc0cee374f5571d9929c9985f463773167e68@changeidReviewed-by:
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Douglas Anderson authored
I would repeat the same commit message that was in commit 5e4b7e82 ("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") but it seems silly to do so when you could just go read that commit. NOTE: this is actually extra terrible because we're missing the 50 MHz rate in the table (see the next patch AKA ("clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2")). That means then when you run an older SD card it'll try to clock it at 100 MHz when it's only specced to run at 50 MHz max. As you can probably guess that doesn't work super well. Signed-off-by:
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Yoshihiro Shimoda authored
Convert Renesas R-Car USB 2.0 clock selector bindings documentation to json-schema. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by:
Geert Uytterhoeven <geert@linux-m68k.org>
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Geert Uytterhoeven authored
There is no reason to keep on using the __raw_{read,write}l() I/O accessors in Renesas ARM driver code. Switch to using the plain {read,write}l() I/O accessors, to have a chance that this works on big-endian. Suggested-by:Arnd Bergmann <arnd@kernel.org> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
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Lad Prabhakar authored
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR driver. Add new clk type CLK_TYPE_GEN3_E3_RPCSRC to register rpcsrc as a fixed clock on R-Car Gen3 E3 (and also RZ/G2E which is identical to E3 SoC), parent and the divider is set based on the register value CPG_RPCCKCR[4:3] which has been set prior to booting the kernel. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201116101002.5986-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
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Geert Uytterhoeven authored
The R-Car V3U clock driver defines the R and OSC clocks using R-Car Gen3 clock types. However, The R-Car V3U clock driver does not use the R-Car Gen3 clock driver core, hence registering the R and OSC clocks fails: renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock osc: -22 renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock r: -22 Fix this by introducing clock definition macros specific to R-Car V3U. Note that rcar_r8a779a0_cpg_clk_register() already handled the related clock types. Drop the now unneeded include of rcar-gen3-cpg.h. Fixes: 17bcc803 ("clk: renesas: cpg-mssr: Add support for R-Car V3U") Signed-off-by: -
Krzysztof Kozlowski authored
The struct cpg_mssr_priv missed proper formatting: drivers/clk/renesas/renesas-cpg-mssr.c:142: warning: cannot understand function prototype: 'struct cpg_mssr_priv ' Signed-off-by:Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201103162435.13689-7-krzk@kernel.orgSigned-off-by:
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Yejune Deng authored
devm_reset_control_array_get_shared() looks more readable Signed-off-by:
Yejune Deng <yejune.deng@gmail.com> Link: https://lore.kernel.org/r/1604375093-6451-1-git-send-email-yejune.deng@gmail.comSigned-off-by:
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Biju Das authored
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2N (R8A774B1) CPG/MSSR driver. Inspired by commit 94e3935b ("clk: renesas: r8a77980: Add RPC clocks"). Signed-off-by:
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Biju Das authored
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2M (R8A774A1) CPG/MSSR driver. Inspired by commit 94e3935b ("clk: renesas: r8a77980: Add RPC clocks"). Signed-off-by:
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Jacopo Mondi authored
Add definitions of the VIN instance clocks for R-Car V3U. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20201016111158.17521-5-jacopo+renesas@jmondi.orgSigned-off-by:
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Jacopo Mondi authored
Add definitions of the CSI-2 receiver clocks for R-Car V3U. Signed-off-by:
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Geert Uytterhoeven authored
Align the clock branch name with other renesas-* branches pulled by subsystem maintainers. Signed-off-by:
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Geert Uytterhoeven authored
When compiling with clang: drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:21: warning: no previous prototype for function 'rcar_r8a779a0_cpg_clk_register' [-Wmissing-prototypes] struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, ^ drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:1: note: declare 'static' if the function is not intended to be used outside of this translation unit struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, ^ static Similarly, with sparse: drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:12: warning: symbol 'rcar_r8a779a0_cpg_clk_register' was not declared. Should it be static? There are no users of rcar_r8a779a0_cpg_clk_register() outside this file, so it should be static. Fixes: 17bcc803 ("clk: renesas: cpg-mssr: Add support for R-Car V3U") Reported-by:kernel test robot <lkp@intel.com> Signed-off-by:
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- 08 Dec, 2020 6 commits
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Manivannan Sadhasivam authored
Add GDSC support to control the power supply of power domains in SDX55 GCC. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201126072844.35370-7-manivannan.sadhasivam@linaro.orgSigned-off-by:
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Manivannan Sadhasivam authored
Add GDSC instances in SDX55 GCC block. Signed-off-by:
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Manivannan Sadhasivam authored
Add support for following clocks maintained by RPMh in SDX55 SoCs. * BI TCXO * RF_CLK1 * RF_CLK1_AO * RF_CLK2 * RF_CLK2_AO * QPIC (Qualcomm Technologies, Inc. Parallel Interface Controller) Signed-off-by:
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Vinod Koul authored
Add compatible for SDX55 RPMHCC and DT include. Signed-off-by:
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Naveen Yadav authored
Add Global Clock Controller (GCC) support for SDX55 SoCs from Qualcomm. Signed-off-by:
Naveen Yadav <naveenky@codeaurora.org> [mani: converted to parent_data, commented critical clocks, cleanups] Signed-off-by:
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Vinod Koul authored
Add device tree bindings for global clock controller on SDX55 SoCs. Signed-off-by:
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- 05 Dec, 2020 1 commit
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Stephen Boyd authored
Merge tag 'clk-v5.11-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung Pull Samsung clk driver updates from Sylwester Nawrocki: - Correction of Kconfig dependencies for better compile test coverage - Refactoring of the PLL clocks driver * tag 'clk-v5.11-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: Prevent potential endless loop in the PLL ops clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
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- 27 Nov, 2020 1 commit
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Colin Ian King authored
There is a spelling mistake in the Kconfig help text. Fix it. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20201126232400.15011-1-colin.king@canonical.comSigned-off-by:
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- 25 Nov, 2020 2 commits
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Thara Gopinath authored
Qualcomm CE clock resource that is managed by BCM is required by crypto driver to access the core clock. Reviewed-by:
Thara Gopinath <thara.gopinath@linaro.org> Link: https://lore.kernel.org/r/20201119155233.3974286-3-thara.gopinath@linaro.orgSigned-off-by:
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Thara Gopinath authored
Add clock id forc CE clock resource which is required to bring up the crypto engine on sdm845. Reviewed-by:
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- 23 Nov, 2020 2 commits
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Sylwester Nawrocki authored
The PLL status polling loops in the set_rate callbacks of some PLLs have no timeout detection and may become endless loops when something goes wrong with the PLL. For some PLLs there is already the ktime API based timeout detection, but it will not work in all conditions when .set_rate gets called. In particular, before the clocksource is initialized or when the timekeeping is suspended. This patch adds a common helper with the PLL status bit polling and timeout detection. For conditions where the timekeeping API should not be used a simple readl_relaxed/cpu_relax() busy loop is added with the iterations limit derived from measurements of readl_relaxed() execution time for various PLL types and Exynos SoCs variants. Actual PLL lock time depends on the P divider value, the VCO frequency and a constant PLL type specific LOCK_FACTOR and can be calculated as lock_time = Pdiv * LOCK_FACTOR / VCO_freq For the ktime API use cases a common timeout value of 20 ms is applied for all the PLLs with an assumption that maximum possible value of Pdiv is 64, maximum possible LOCK_FACTOR value is 3000 and minimum VCO frequency is 24 MHz. Link: https://lore.kernel.org/r/20201120155731.26898-1-s.nawrocki@samsung.comReviewed-by:
Sylwester Nawrocki <s.nawrocki@samsung.com>
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Krzysztof Kozlowski authored
So far all Exynos, S3C64xx and S5Pv210 clock units were selected by respective SOC/ARCH Kconfig option. On a kernel built for selected SoCs, this allowed to build only limited set of matching clock drivers. However compile testing was not possible in such case as Makefile object depends on SOC/ARCH option. Add separate Kconfig options for each of them to be able to compile test. Link: https://lore.kernel.org/r/20201119164509.754851-1-krzk@kernel.orgSigned-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by:
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- 14 Nov, 2020 9 commits
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Dmitry Baryshkov authored
On SM8250 MMCX power domain is required to access MMDS_GDSC registers. This power domain is expressed as mmcx-supply regulator property. Use this regulator as MDSS_GDSC supply. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20201023131925.334864-6-dmitry.baryshkov@linaro.orgSigned-off-by:
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Jerome Brunet authored
Until now, nothing was done to unregister the dvfs clock notifiers of the Amlogic g12 SoC family. This is not great but this driver was not really expected to be unloaded. With the ongoing effort to build everything as module for this platform, this needs to be cleanly handled. Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201021163847.595189-3-jbrunet@baylibre.comSigned-off-by:
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Jerome Brunet authored
Add a memory managed variant of clk_notifier_register() to make life easier on clock consumers using notifiers Signed-off-by:
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Jerome Brunet authored
g12 clock controller used __clk_lookup() to get struct clk from a struct clk_hw. This type of hack is no longer required as CCF now provides the necessary functions to get this. Signed-off-by:
Kevin Hilman <khilman@baylibre.com> Signed-off-by:
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Jerome Brunet authored
clk_register() is deprecated. Using 'clk' member of struct clk_hw is discouraged. With this constraint, it is difficult for driver to register clocks using the clk_hw API and then use the clock with the consumer API This adds a simple helper, clk_hw_get_clk(), to get a struct clk from a struct clk_hw. Like other clk_get() variant, each call to this helper must be balanced with a call to clk_put(). To make life easier on the consumers, a memory managed version is provided as well. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
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Jerome Brunet authored
In clk-devres.c, devm_clk_release() is used to call clk_put() memory managed clock. In clk.c the same name, in a different scope is used to call clk_unregister(). As it stands, it is not really a problem but it does not readability, especially if we need to call clk_put() on managed clock in clk.c Signed-off-by:
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Lukas Bulwahn authored
make clang-analyzer on x86_64 defconfig caught my attention with: drivers/clk/clk.c:423:19: warning: Value stored to 'parent' during its initialization is never read [clang-analyzer-deadcode.DeadStores] struct clk_core *parent = ERR_PTR(-ENOENT); ^ Commit fc0c209c ("clk: Allow parents to be specified without string names") introduced clk_core_fill_parent_index() with this unneeded dead-store initialization. So, simply remove this unneeded dead-store initialization to make clang-analyzer happy. As compilers will detect this unneeded assignment and optimize this anyway, the resulting object code is identical before and after this change. No functional change. No change to object code. Signed-off-by:Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20201106094820.30167-1-lukas.bulwahn@gmail.comReviewed-by:
Nathan Chancellor <natechancellor@gmail.com> Signed-off-by:
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Stephen Boyd authored
Let's call pm_runtime_get() here instead of calling the PM clk APIs directly. This avoids a compilation problem on CONFIG_PM=n where the pm_clk_runtime_{resume,suspend}() functions don't exist and covers the intent, i.e. enable the clks for this device so we can program PLL settings. Reported-by:Randy Dunlap <rdunlap@infradead.org> Reported-by:
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Dan Carpenter authored
Clean up the first driver if the second driver can't be registered. Fixes: 4ee9fe3e ("clk: qcom: lpass-sc7180: Disentangle the two clock devices") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20201113101419.GC168908@mwandaReviewed-by:
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