- 26 May, 2022 2 commits
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Ashutosh Dixit authored
Expose new sysfs to program and retrieve media freq factor. Factor values of 0 (dynamic), 0.5 and 1.0 are supported via a u8.8 fixed point representation (corresponding to integer values of 0, 128 and 256 respectively). Media freq factor is converted to media_ratio_mode for GuC. It is programmed into GuC using H2G SLPC interface. It is retrieved from GuC through a register read. A cached media_ratio_mode is maintained to preserve set values across GuC resets. This patch adds the following sysfs files to gt/gtN sysfs: * media_freq_factor * media_freq_factor.scale v2: Minor wording change in drm_warn (Tvrtko) Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
Dale B Stimson <dale.b.stimson@intel.com> Signed-off-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by:
Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/7ad7578335d8af9cba047b4bcf33d1887453d2e1.1653484574.git.ashutosh.dixit@intel.com
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Alan Previn authored
Fix our pointer offset usage in error_state_read when there is no i915_gpu_coredump but buf offset is non-zero. This fixes a kernel page fault can happen when multiple tests are running concurrently in a loop and one is producing engine resets and consuming the i915 error_state dump while the other is forcing full GT resets. (takes a while to trigger). The dmesg call trace: [ 5590.803000] BUG: unable to handle page fault for address: ffffffffa0b0e000 [ 5590.803009] #PF: supervisor read access in kernel mode [ 5590.803013] #PF: error_code(0x0000) - not-present page [ 5590.803016] PGD 5814067 P4D 5814067 PUD 5815063 PMD 109de4067 PTE 0 [ 5590.803022] Oops: 0000 [#1] PREEMPT SMP NOPTI [ 5590.803026] CPU: 5 PID: 13656 Comm: i915_hangman Tainted: G U 5.17.0-rc5-ups69-guc-err-capt-rev6+ #136 [ 5590.803033] Hardware name: Intel Corporation Alder Lake Client Platform/AlderLake-M LP4x RVP, BIOS ADLPFWI1.R00. 3031.A02.2201171222 01/17/2022 [ 5590.803039] RIP: 0010:memcpy_erms+0x6/0x10 [ 5590.803045] Code: fe ff ff cc eb 1e 0f 1f 00 48 89 f8 48 89 d1 48 c1 e9 03 83 e2 07 f3 48 a5 89 d1 f3 a4 c3 66 0f 1f 44 00 00 48 89 f8 48 89 d1 <f3> a4 c3 0f 1f 80 00 00 00 00 48 89 f8 48 83 fa 20 72 7e 40 38 fe [ 5590.803054] RSP: 0018:ffffc90003a8fdf0 EFLAGS: 00010282 [ 5590.803057] RAX: ffff888107ee9000 RBX: ffff888108cb1a00 RCX: 0000000000000f8f [ 5590.803061] RDX: 0000000000001000 RSI: ffffffffa0b0e000 RDI: ffff888107ee9071 [ 5590.803065] RBP: 0000000000000000 R08: 0000000000000001 R09: 0000000000000001 [ 5590.803069] R10: 0000000000000001 R11: 0000000000000002 R12: 0000000000000019 [ 5590.803073] R13: 0000000000174fff R14: 0000000000001000 R15: ffff888107ee9000 [ 5590.803077] FS: 00007f62a99bee80(0000) GS:ffff88849f880000(0000) knlGS:0000000000000000 [ 5590.803082] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 5590.803085] CR2: ffffffffa0b0e000 CR3: 000000010a1a8004 CR4: 0000000000770ee0 [ 5590.803089] PKRU: 55555554 [ 5590.803091] Call Trace: [ 5590.803093] <TASK> [ 5590.803096] error_state_read+0xa1/0xd0 [i915] [ 5590.803175] kernfs_fop_read_iter+0xb2/0x1b0 [ 5590.803180] new_sync_read+0x116/0x1a0 [ 5590.803185] vfs_read+0x114/0x1b0 [ 5590.803189] ksys_read+0x63/0xe0 [ 5590.803193] do_syscall_64+0x38/0xc0 [ 5590.803197] entry_SYSCALL_64_after_hwframe+0x44/0xae [ 5590.803201] RIP: 0033:0x7f62aaea5912 [ 5590.803204] Code: c0 e9 b2 fe ff ff 50 48 8d 3d 5a b9 0c 00 e8 05 19 02 00 0f 1f 44 00 00 f3 0f 1e fa 64 8b 04 25 18 00 00 00 85 c0 75 10 0f 05 <48> 3d 00 f0 ff ff 77 56 c3 0f 1f 44 00 00 48 83 ec 28 48 89 54 24 [ 5590.803213] RSP: 002b:00007fff5b659ae8 EFLAGS: 00000246 ORIG_RAX: 0000000000000000 [ 5590.803218] RAX: ffffffffffffffda RBX: 0000000000100000 RCX: 00007f62aaea5912 [ 5590.803221] RDX: 000000000008b000 RSI: 00007f62a8c4000f RDI: 0000000000000006 [ 5590.803225] RBP: 00007f62a8bcb00f R08: 0000000000200010 R09: 0000000000101000 [ 5590.803229] R10: 0000000000000001 R11: 0000000000000246 R12: 0000000000000006 [ 5590.803233] R13: 0000000000075000 R14: 00007f62a8acb010 R15: 0000000000200000 [ 5590.803238] </TASK> [ 5590.803240] Modules linked in: i915 ttm drm_buddy drm_dp_helper drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops prime_numbers nfnetlink br_netfilter overlay mei_pxp mei_hdcp x86_pkg_temp_thermal coretemp kvm_intel snd_hda_codec_hdmi snd_hda_intel snd_intel_dspcfg snd_hda_codec snd_hwdep snd_hda_core snd_pcm mei_me mei fuse ip_tables x_tables crct10dif_pclmul e1000e crc32_pclmul ptp i2c_i801 ghash_clmulni_intel i2c_smbus pps_core [last unloa ded: ttm] [ 5590.803277] CR2: ffffffffa0b0e000 [ 5590.803280] ---[ end trace 0000000000000000 ]--- Fixes: 0e39037b ("drm/i915: Cache the error string") Signed-off-by:Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by:
John Harrison <John.C.Harrison@Intel.com> Signed-off-by:
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- 25 May, 2022 1 commit
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Matt Roper authored
PVC also has a hwconfig table. Actually the current expectation is that all future platforms will have hwconfig, so let's just change the condition to an IP version check so that we don't need to keep updating this for each new platform that shows up. Cc: John Harrison <john.c.harrison@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
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- 24 May, 2022 7 commits
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Balasubramani Vivekanandan authored
ADL-N being a subplatform of ADL-P, it lacks support for hwconfig table. Explicit check added to skip ADL-N. Signed-off-by:
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by:
Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by:
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Daniele Ceraolo Spurio authored
Disable HuC loading since it is not used on these platforms. Cc: Stuart Summers <stuart.summers@intel.com> Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by:
Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220511060228.1179450-6-matthew.d.roper@intel.com
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Matt Roper authored
Initialize ADS system info to reflect the availability of new BCS engines Original-author: CQ Tang Cc: Stuart Summers <stuart.summers@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Signed-off-by:
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Stuart Summers authored
Although we already strip 3D-specific flags from PIPE_CONTROL instructions when submitting to a compute engine, there are some additional flags that need to be removed when the platform as a whole lacks a 3D pipeline. Add those restrictions here. v2: - Replace LACKS_3D_PIPELINE checks with !HAS_3D_PIPELINE and add has_3d_pipeline to all platforms except PVC. (Lucas) Bspec: 47112 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Stuart Summers <stuart.summers@intel.com> Signed-off-by:
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Matt Roper authored
Add PVC's forcewake ranges. v2: - Drop replicated comment completely; move general cleanup of the documentation to a separate patch. Bspec: 67609 Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Stuart Summers <stuart.summers@intel.com> Signed-off-by:
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Matt Roper authored
Let's reorganize some of the forcewake/shadow handling in intel_uncore.c and consolidate the cargo-cult comments on each table into more general comments that apply to all tables. We'll probably move forcewake handling to its own dedicated file in the near future and further enhance this with true kerneldoc. But this is a good intermediate step to help clarify the behavior a bit. Cc: Stuart Summers <stuart.summers@intel.com> Signed-off-by:
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Bommu Krishnaiah authored
Update the selftest to include Tile 4 mode and switch to Tile 4 on platforms that supports Tile 4 but no Tile Y and vice versa. Also switch to XY_FAST_COPY_BLT on platforms that supports it. v4: update commit message to reflect the code changes properly. v3: add a function to find X-tile availability for a platform. v2: disable Tile X for iGPU in fastblit and fix checkpath --strict warnings. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5879Signed-off-by:Bommu Krishnaiah <krishnaiah.bommu@intel.com> Co-developed-by:
Nirmoy Das <nirmoy.das@intel.com> Signed-off-by:
Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220516082015.32020-1-nirmoy.das@intel.com
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- 23 May, 2022 1 commit
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Tvrtko Ursulin authored
Merge tag 'drm-intel-next-2022-05-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-intel-gt-next drm/i915 drm-intel-next -> drm-intel-gt-next cross-merge sync Signed-off-by:
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- 20 May, 2022 10 commits
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Dale B Stimson authored
Some dGfx pcode commands take additional sub-commands and parameters. Add a couple of helpers to help formatting these commands to improve code readability. v2: Fixed commit author (Rodrigo) v3: Function rename and convert to new uncore interface for pcode functions Remove unnecessary #define's (Andi) v4: Another function rename Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: -
Ashutosh Dixit authored
Each gt contains an independent instance of pcode. Extend pcode functions to interface with pcode on different gt's. To avoid creating dependency of display functionality on intel_gt, pcode function interfaces are exposed in terms of uncore rather than intel_gt. Callers have been converted to pass in the appropritate (i915 or intel_gt) uncore to the pcode functions. v2: Expose pcode functions in terms of uncore rather than gt (Jani/Rodrigo) v3: Retain previous function names to eliminate needless #defines (Rodrigo) v4: Move out i915_pcode_init() to a separate patch (Tvrtko) Remove duplicated drm_err/drm_dbg from intel_pcode_init() (Tvrtko) Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: -
Ashutosh Dixit authored
Media ratio mode (the ability for media IP to work at a different frequency from the GT) is available for a subset of dGfx platforms supporting GuC/SLPC. Introduce 'has_media_ratio_mode' flag in intel_device_info to identify these platforms and set it for XEHPSDV and DG2/ATS-M. Signed-off-by:
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Tvrtko Ursulin authored
This reverts commit 222ff6db. Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220519090802.1294691-8-tvrtko.ursulin@linux.intel.com
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Tvrtko Ursulin authored
This reverts commit 218076ab. Signed-off-by:
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Tvrtko Ursulin authored
This reverts commit 922abe4d. Signed-off-by:
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Tvrtko Ursulin authored
This reverts commit b6411373. Signed-off-by:
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Tvrtko Ursulin authored
This reverts commit efd01cd3. Signed-off-by:
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Tvrtko Ursulin authored
This reverts commit eb86f645. Signed-off-by:
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Tvrtko Ursulin authored
This reverts commit b15a7357. Signed-off-by:
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- 19 May, 2022 4 commits
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Swathi Dhanavanthri authored
Signed-off-by:
Swathi Dhanavanthri <swathi.dhanavanthri@intel.com> Reviewed-by:
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Swathi Dhanavanthri authored
Signed-off-by:
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Borislav Petkov authored
Fix: In file included from <command-line>:0:0: drivers/gpu/drm/i915/gt/uc/intel_guc.c: In function ‘intel_guc_send_mmio’: ././include/linux/compiler_types.h:352:38: error: call to ‘__compiletime_assert_1047’ \ declared with attribute error: FIELD_PREP: mask is not constant _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) and other build errors due to shift overflowing values. See https://lore.kernel.org/r/YkwQ6%2BtIH8GQpuct@zn.tnic for the gory details as to why it triggers with older gccs only. v2 by Jani: - Drop the i915_reg.h changes Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Ruiqi GONG <gongruiqi1@huawei.com> Cc: Randy Dunlap <rdunlap@infradead.org> Signed-off-by:Borislav Petkov <bp@suse.de> Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220518113315.1305027-2-jani.nikula@intel.com
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Jani Nikula authored
Use REG_GENMASK() and REG_FIELD_PREP() to avoid errors due to -fsanitize=shift. References: https://lore.kernel.org/r/20220405151517.29753-12-bp@alien8.deReported-by:
Ruiqi GONG <gongruiqi1@huawei.com> Cc: Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220518113315.1305027-1-jani.nikula@intel.com
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- 18 May, 2022 3 commits
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Andi Shyti authored
The INTEL_GT_RPS_SYSFS_ATTR was creating to different structures but. When called with the "static" keyword this is affecting only the first structure, while the second is created as non static. Move the static keyword inside the macros to affect both the structures. Reported-by:
Jani Nikula <jani.nikula@linux.intel.com> Fixes: 56a709cf ("drm/i915/gt: Create per-tile RPS sysfs interfaces") Signed-off-by:
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Maarten Lankhorst authored
When removing short term pins, I've changed the the batch buffer pinning for relocation to use __i915_vma_pin, because i915_gem_object_ggtt_pin_ww was destroying the old vma. This caused regressions, because the functions are not identical. Fix the regressions by calling i915_gem_object_ggtt_pin_ww() again on ggtt-only platforms, but only if the batch can be pinned without being moved. Fixes: b5cfe6f7 ("drm/i915: Remove short-term pins from execbuf, v6.") Cc: Matthew Auld <matthew.auld@intel.com> Reported-by:
Mateusz Jończyk <mat.jonczyk@o2.pl> Tested-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by:
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Ramalingam C authored
Capture the impact of memory region preference list of the objects, on their memory residency and Flat-CCS capability. v2: Fix the Flat-CCS capability of an obj with {lmem, smem} preference list [Thomas] v3: Reworded the doc [Matt] v4: Fixed Typos and spelling mistakes [Tvrtko, Joonas] Signed-off-by:Ramalingam C <ramalingam.c@intel.com> cc: Matthew Auld <matthew.auld@intel.com> cc: Thomas Hellstrom <thomas.hellstrom@linux.intel.com> cc: Daniel Vetter <daniel.vetter@ffwll.ch> cc: Jon Bloomfield <jon.bloomfield@intel.com> cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> cc: Kenneth Graunke <kenneth@whitecape.org> cc: mesa-dev@lists.freedesktop.org cc: Jordan Justen <jordan.l.justen@intel.com> cc: Tony Ye <tony.ye@intel.com> Reviewed-by:
Jordan Justen <jordan.l.justen@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220502141508.2327-1-ramalingam.c@intel.com
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- 17 May, 2022 4 commits
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Alan Previn authored
GuC error capture blurts some debug messages about empty register lists for certain register types on engines during firmware initialization. These are not errors or warnings, so get rid of them. Signed-off-by:
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Nirmoy Das authored
Currently we just fatally crash during module load if we encounter small-BAR configuration on DG2. We have most of the support already, but we lack the final uAPI bits to tie it all together. Signed-off-by:
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Nirmoy Das authored
Determine lmem_size using ADDR_RANGE register so that lmem_setup() works on platform with small-bar as well. Signed-off-by:
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Nirmoy Das authored
Caller of setup_lmem() ignores -ENODEV but failing to setup lmem on dGPU isn't ignorable error. Signed-off-by:
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- 16 May, 2022 3 commits
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Jouni Högander authored
Current update area calculation is not handling situation where e.g. cursor plane is fully or partially outside pipe area. Fix this by checking damage area against pipe_src area using drm_rect_intersect. v2: Set x1 and x2 in damaged_area initialization v3: Move drm_rect_intersect into clip_area_update v4: draw_area -> pipe_src Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5440 Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
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Jouni Högander authored
Currently we have some corner cases where area calculation fails. For these sel fetch area calculation ends up having update area as y1 = 0, y2 = 4. Instead of these values safer option is full update. One of such for example is big fb with offset. We don't have usable offset in psr2_sel_fetch_update. Currently it's open what is the proper way to fix this corner case. Use full update for now. v2: Commit message modified v3: Print out debug info once when area calculation fails v4: Use drm_info_once v5: pipeA -> "pipe %c", pipe_name(crtc-pipe) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Anshuman Gupta authored
RPM suspend/resume also supported on gfx platforms which doesn't have kms support and even on platforms without any connected display panel. There is no good reason to log rpm suspend/resume debug message with drm_dbg_kms() therefore changing it to drm_dbg(). Signed-off-by:
Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by:
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- 13 May, 2022 4 commits
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Vinay Belgaumkar authored
To avoid false positives in error injection cases. Signed-off-by:
Vinay Belgaumkar <vinay.belgaumkar@intel.com> Reviewed-by:
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Jani Nikula authored
Need to use pipe_name(pipe) instead of pipe directly. Fixes: 1f31e35f ("drm/i915/audio: unify audio codec enable/disable debug logging") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Nathan Chancellor authored
When an attribute group is created with sysfs_create_group(), the ->sysfs_ops() callback is set to kobj_sysfs_ops, which sets the ->show() callback to kobj_attr_show(). kobj_attr_show() uses container_of() to get the ->show() callback from the attribute it was passed, meaning the ->show() callback needs to be the same type as the ->show() callback in 'struct kobj_attribute'. However, show_dynamic_id() has the type of the ->show() callback in 'struct device_attribute', which causes a CFI violation when opening the 'id' sysfs node under drm/card0/metrics. This happens to work because the layout of 'struct kobj_attribute' and 'struct device_attribute' are the same, so the container_of() cast happens to allow the ->show() callback to still work. Change the type of show_dynamic_id() to match the ->show() callback in 'struct kobj_attributes' and update the type of sysfs_metric_id to match, which resolves the CFI violation. Fixes: f89823c2 ("drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interface") Signed-off-by:
Nathan Chancellor <nathan@kernel.org> Reviewed-by:
Kees Cook <keescook@chromium.org> Reviewed-by:
Sami Tolvanen <samitolvanen@google.com> Signed-off-by:
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Anusha Srivatsa authored
Bspec has added some steps that check forDMC MMIO range before programming them v2: Fix for CI v3: move register defines to .h (Anusha) - Check MMIO restrictions per pipe - Add MMIO restricton for v1 dmc header as well (Lucas) v4: s/_PICK/_PICK_EVEN and use it only for Pipe DMC scenario. - clean up sanity check logic.(Lucas) - Add MMIO range for RKL as well.(Anusha) v5: Use DISPLAY_VER instead of per platform check (Lucas) BSpec: 49193 Cc: stable@vger.kernel.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by:
Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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- 12 May, 2022 1 commit
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Umesh Nerlige Ramappa authored
There are 2 ways an engine can get reset in i915 and the method of reset affects how KMD labels a context as guilty/innocent. (1) GuC initiated engine-reset: GuC resets a hung engine and notifies KMD. The context that hung on the engine is marked guilty and all other contexts are innocent. The innocent contexts are resubmitted. (2) GT based reset: When an engine heartbeat fails to tick, KMD initiates a gt/chip reset. All active contexts are marked as guilty and discarded. In order to correctly mark the contexts as guilty/innocent, pass a mask of engines that were reset to __guc_reset_context. Fixes: eb5e7da7 ("drm/i915/guc: Reset implementation for new GuC interface") Signed-off-by:
Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by:
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