- 12 Jan, 2022 1 commit
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Stephen Boyd authored
* clk-doc: clk: Gemini: fix struct name in kernel-doc clk: zynq: pll: Fix kernel-doc warnings clk: imx: pllv1: fix kernel-doc notation for struct clk_pllv1 * clk-renesas: (31 commits) clk: renesas: r9a07g044: Add GPU clock and reset entries clk: renesas: r9a07g044: Add mux and divider for G clock clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro clk: renesas: cpg-mssr: Add support for R-Car S4-8 clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions dt-bindings: power: Add r8a779f0 SYSC power domain definitions clk: renesas: r9a07g044: Add TSU clock and reset entry mmc: renesas_sdhi: Simplify an expression mmc: renesas_sdhi: Use devm_clk_get_optional() to obtain CD clock dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0 clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple() clk: renesas: cpg-mssr: Check return value of pm_genpd_init() clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple() clk: renesas: rzg2l: Check return value of pm_genpd_init() clk: renesas: r9a07g044: Add RSPI clock and reset entries clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV clk: renesas: rzg2l: Add CPG_PL1_DDIV macro mmc: renesas_sdhi: Parse DT for SDnH mmc: renesas_sdhi: Use dev_err_probe when getting clock fails ... * clk-at91: clk: lan966x: Extend lan966x clock driver for clock gating support dt-bindings: clock: lan966x: Extend includes with clock gates dt-bindings: clock: lan966x: Extend for clock gate support clk: gate: Add devm_clk_hw_register_gate() clk: lan966x: Add lan966x SoC clock driver dt-bindings: clock: lan966x: Add LAN966X Clock Controller dt-bindings: clock: lan966x: Add binding includes for lan966x SoC clock IDs * clk-cleanup: clk: stm32mp1: remove redundant assignment to pointer data clk: __clk_core_init() never takes NULL clk: clk_core_get() can also return NULL clk/ti/adpll: Make const pointer error a static const array * clk-debugfs: clk: Enable/Disable runtime PM for clk_summary clk: Emit a stern warning with writable debugfs enabled clk: Add write operation for clk_parent debugfs node
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- 06 Jan, 2022 1 commit
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Taniya Das authored
The registers for some clocks in the SOC area, which are under the power domain are required to be enabled before accessing them. During the clk_summary if the power-domains are not enabled they could result into NoC errors. Thus ensure the register access of the clock controller is done with pm_untime_get/put functions. Signed-off-by:
Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1640018638-19436-3-git-send-email-tdas@codeaurora.orgSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 29 Dec, 2021 1 commit
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Stephen Boyd authored
Merge tag 'renesas-clk-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC - Add GPU clock and resets on Renesas RZ/G2L - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a07g044: Add GPU clock and reset entries clk: renesas: r9a07g044: Add mux and divider for G clock clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro clk: renesas: cpg-mssr: Add support for R-Car S4-8 clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions dt-bindings: power: Add r8a779f0 SYSC power domain definitions
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- 16 Dec, 2021 1 commit
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Colin Ian King authored
The pointer data is being initialized with a value and a few lines later on being re-assigned the same value, so this re-assignment is redundant. Clean up the code and remove it. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20211126221239.1100960-1-colin.i.king@gmail.comSigned-off-by:
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- 10 Dec, 2021 5 commits
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Stephen Boyd authored
We don't want vendors to be enabling this part of the clk code and shipping it to customers. Exposing the ability to change clk frequencies and parents via debugfs is potentially damaging to the system if folks don't know what they're doing. Emit a strong warning so that the message is clear: don't enable this outside of development systems. Fixes: 37215da5 ("clk: Add support for setting clk_rate via debugfs") Cc: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20211210014237.2130300-1-sboyd@kernel.orgSigned-off-by:
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Sam Protsenko authored
Useful for testing mux clocks. One can write the index of the parent to be set into clk_parent node, starting from 0. Example # cd /sys/kernel/debug/clk/mout_peri_bus # cat clk_possible_parents dout_shared0_div4 dout_shared1_div4 # cat clk_parent dout_shared0_div4 # echo 1 > clk_parent # cat clk_parent dout_shared1_div4 CLOCK_ALLOW_WRITE_DEBUGFS has to be defined in drivers/clk/clk.c in order to use this feature. Signed-off-by:Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Fabio Estevam <festevam@gmail.com> Acked-by:
Michael Turquette <mturquette@baylibre.com> Link: https://lore.kernel.org/r/20211013172042.10884-1-semen.protsenko@linaro.org [sboyd@kernel.org: Collapse ifdefs] Signed-off-by:
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Stephen Boyd authored
The only caller of __clk_core_init() allocates the pointer and checks the allocation for NULL so this check is impossible. Remove it. Signed-off-by:
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Stephen Boyd authored
Nothing stops a clk controller from registering an OF clk provider before registering those clks with the clk framework. This is not great but we deal with it in the clk framework by refusing to hand out struct clk pointers when 'hw->core' is NULL, the indication that clk_register() has been called. Within clk_core_fill_parent_index() we considered this case when a clk_hw pointer is referenced directly by filling in the parent cache with an -EPROBE_DEFER pointer when the core pointer is NULL. When we lookup a parent with clk_core_get() we don't care about the return value being NULL though, because that was considered largely impossible, but it's been proven now that it can be NULL if two clk providers are probing in parallel and the parent provider has been registered before the clk has. Let's check for NULL here as well and treat it the same as direct clk_hw references. Signed-off-by:
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Colin Ian King authored
Make const pointer error a static const array, removes a dereference and shrinks object code a little. Signed-off-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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- 09 Dec, 2021 1 commit
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git://git.kernel.org/pub/scm/linux/kernel/git/at91/linuxStephen Boyd authored
Pull AT91 clk driver updates from Nicolas Ferre: - Lan966x Generic Clock Controller driver and associated DT bindings - Lan966x clock driver extended to support clock gating * tag 'clk-at91-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: lan966x: Extend lan966x clock driver for clock gating support dt-bindings: clock: lan966x: Extend includes with clock gates dt-bindings: clock: lan966x: Extend for clock gate support clk: gate: Add devm_clk_hw_register_gate() clk: lan966x: Add lan966x SoC clock driver dt-bindings: clock: lan966x: Add LAN966X Clock Controller dt-bindings: clock: lan966x: Add binding includes for lan966x SoC clock IDs
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- 08 Dec, 2021 14 commits
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Horatiu Vultur authored
Extend the clock driver to add support also for clock gating. The following peripherals can be gated: UHPHS, UDPHS, MCRAMC, HMATRIX. Signed-off-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Acked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by:
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Horatiu Vultur authored
On lan966x it is allow to control the clock to some peripherals like USB. So extend the include file with these clocks. Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Horatiu Vultur authored
Allow to add an optional resource to be able to access the clock gate registers. Signed-off-by:
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Horatiu Vultur authored
Add devm_clk_hw_register_gate() - devres-managed version of clk_hw_register_gate() Suggested-by:
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Kavyasree Kotagiri authored
This adds Generic Clock Controller driver for lan966x SoC. Lan966x clock controller contains 3 PLLs - cpu_clk, ddr_clk and sys_clk. It generates and supplies clock to various peripherals within SoC. Register settings required to provide GCK clocking to a peripheral is as below: GCK_SRC_SEL = Select clock source. GCK_PRESCALER = Set divider value. GCK_ENA = 1 - Enable GCK clock. Signed-off-by:
Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Co-developed-by:
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Kavyasree Kotagiri authored
This adds the DT bindings documentation for lan966x SoC generic clock controller. Signed-off-by:
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Kavyasree Kotagiri authored
LAN966X supports 14 clock outputs for its peripherals. This include file is introduced to use identifiers for clocks. Signed-off-by:
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Biju Das authored
Add GPU clock and reset entries to CPG driver. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211203115154.31864-4-biju.das.jz@bp.renesas.comSigned-off-by:
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Biju Das authored
G clock is sourced from PLL3 and PLL6. The output of the mux is connected to divider. This patch adds a mux and divider for getting different rates from this clock sources. Signed-off-by:
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Biju Das authored
Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree mentioned in the hardware manual(Rev.1.00 Sep, 2021). Signed-off-by:
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Yoshihiro Shimoda authored
Initial CPG support for R-Car S4-8 (r8a779f0). Inspired by patches in the BSP by LUU HOAI. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-10-yoshihiro.shimoda.uh@renesas.comSigned-off-by:
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Geert Uytterhoeven authored
Renesas R-Car S4-8 DT Binding Definitions Clock and Power Domain definitions for the Renesas R-Car S4-8 (R8A77FA0) SoC, shared by driver and DT source files.
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Yoshihiro Shimoda authored
According to the official website [1], the R-Car V3U SoC is based on the R-Car Gen4 architecture. So, introduce R-Car Gen4 CPG driver. [1] https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-drivingSigned-off-by:
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Stephen Boyd authored
Merge tag 'renesas-clk-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and thermal (TSU) clocks and resets on RZ/G2L - Rework SDHI clock handling in the R-Car Gen3 and RZ/G2 clock drivers, and in the Renesas SDHI driver - Make the Cortex-A55 (I) clock on RZ/G2L programmable, - Document support for the new R-Car S4-8 (R8A779F0) SoC - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (24 commits) clk: renesas: r9a07g044: Add TSU clock and reset entry mmc: renesas_sdhi: Simplify an expression mmc: renesas_sdhi: Use devm_clk_get_optional() to obtain CD clock dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0 clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple() clk: renesas: cpg-mssr: Check return value of pm_genpd_init() clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple() clk: renesas: rzg2l: Check return value of pm_genpd_init() clk: renesas: r9a07g044: Add RSPI clock and reset entries clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV clk: renesas: rzg2l: Add CPG_PL1_DDIV macro mmc: renesas_sdhi: Parse DT for SDnH mmc: renesas_sdhi: Use dev_err_probe when getting clock fails clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRST clk: renesas: rcar-gen3: Switch to new SD clock handling mmc: renesas_sdhi: Flag non-standard SDnH handling for V3M clk: renesas: r8a779a0: Add SDnH clock to V3U clk: renesas: rcar-gen3: Add SDnH clock clk: renesas: rcar-gen3: Add dummy SDnH clock clk: renesas: r9a07g044: Add OSTM clock and reset entries ...
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- 07 Dec, 2021 2 commits
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Yoshihiro Shimoda authored
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car S4-8 (R8A779F0) SoC. Signed-off-by:
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Yoshihiro Shimoda authored
Add power domain indices for R-Car S4-8 (r8a779f0). Signed-off-by:
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- 03 Dec, 2021 3 commits
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Randy Dunlap authored
Fix a typo in the struct name in the kernel-doc notation so that kernel-doc won't complain about it. Fixes this warning: drivers/clk/clk-gemini.c:64: warning: expecting prototype for struct gemini_data_data. Prototype was for struct gemini_gate_data instead Fixes: 846423f9 ("clk: Add Gemini SoC clock controller") Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Reported-by:
kernel test robot <lkp@intel.com> Cc: linux-clk@vger.kernel.org Link: https://lore.kernel.org/r/20211120062719.21395-1-rdunlap@infradead.orgReviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Shubhrajyoti Datta authored
Fix the following kernel-doc warning drivers/clk/zynq/pll.c:15: warning: missing initial short description on line: * struct zynq_pll drivers/clk/zynq/pll.c:96: warning: No description found for return value of 'zynq_pll_is_enabled' drivers/clk/zynq/pll.c:116: warning: No description found for return value of 'zynq_pll_enable' drivers/clk/zynq/pll.c:187: warning: No description found for return value of 'clk_register_zynq_pll' Signed-off-by:
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Link: https://lore.kernel.org/r/9929a56462bfdd491c43c233abc4341fc14dac1d.1637139796.git.shubhrajyoti.datta@xilinx.comSigned-off-by:
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Randy Dunlap authored
Convert struct clk_pllv1 comments to kernel-doc notation and move them below the MFN_* macros. Fixes this kernel-doc warning: drivers/clk/imx/clk-pllv1.c:12: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * pll v1 Fixes: 2af9e6db ("ARM i.MX: Add common clock support for pllv1") Fixes: a5947903 ("ARM: imx: pllv1: Fix PLL calculation for i.MX27") Signed-off-by:
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- 26 Nov, 2021 3 commits
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Biju Das authored
Add TSU clock and reset entry to CPG driver. Signed-off-by:
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Wolfram Sang authored
We already have 'quirks', no need to go via 'priv'. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by:
Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20211117103850.28397-1-wsa+renesas@sang-engineering.comSigned-off-by:
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Geert Uytterhoeven authored
Use the existing devm_clk_get_optional() helper to obtain the optional Card Detect clock, instead of open-coding the same operation. a side effect, real errors will now be handled correctly instead of being ignored. Signed-off-by:
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- 19 Nov, 2021 8 commits
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Yoshihiro Shimoda authored
Add binding documentation for the R-Car S4-8 (R8A779F0) Clock Pulse Generator. Signed-off-by:
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Lad Prabhakar authored
of_genpd_add_provider_simple() might fail, this patch makes sure we check the return value of of_genpd_add_provider_simple() by propagating the return value to the caller of cpg_mssr_add_clk_domain(). Signed-off-by:
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Lad Prabhakar authored
Make sure we check the return value of pm_genpd_init() which might fail. Also add a devres action to remove the power-domain in-case the probe callback fails further down in the code flow. Signed-off-by:
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Lad Prabhakar authored
of_genpd_add_provider_simple() might fail, this patch makes sure we check the return value of of_genpd_add_provider_simple() by propagating the return value to the caller of rzg2l_cpg_add_clk_domain(). Fixes: ef3c613c ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by:
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Lad Prabhakar authored
Make sure we check the return value of pm_genpd_init() which might fail. Also add a devres action to remove the power-domain in-case the probe callback fails further down in the code flow. Fixes: ef3c613c ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by:
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Lad Prabhakar authored
Add RSPI{0,1,2} clock and reset entries to CPG driver. Signed-off-by: -
Biju Das authored
Core clock "I" is sourced from CPG_PL1_DDIV divider as per HW manual Rev.1.00. This patch adds clock divider table "dtable_1_8" and switches to DEF_DIV for "I" clock. Signed-off-by:
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Biju Das authored
Core clock "I" is sourced from CPG_PL1_DDIV which controls CPU frequency. Define CPG_PL1_DDIV, so that we can register it as a clock divider in later patch. Signed-off-by:
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