1. 11 Jun, 2015 12 commits
  2. 10 Jun, 2015 6 commits
    • Shawn Guo's avatar
      MAINTAINERS: update Shawn's email to use kernel.org one · 7609ea2a
      Shawn Guo authored
      Update my mailbox to use kernel.org one for handling kernel community
      maintenance traffic.
      Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
      Signed-off-by: default avatarKevin Hilman <khilman@linaro.org>
      7609ea2a
    • Kevin Hilman's avatar
      Merge tag 'imx-soc-4.2' of... · 3e0d0b81
      Kevin Hilman authored
      Merge tag 'imx-soc-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
      
      The i.MX SoC updates for 4.2:
       - Add new SoC i.MX7D support, which integrates two Cortex-A7 and one
         Cortex-M4 cores.
       - Support suspend from IRAM on i.MX53, so that DDR pins can be set to
         high impedance for more power saving during suspend.
       - Move i.MX clock drivers from arch/arm/mach-imx to drivers/clk/imx.
       - Move i.MX GPT timer driver from arch/arm/mach-imx into
         drivers/clocksource.
       - A couple of clock driver update for VF610 and i.MX6Q.
       - A few random code correction and improvement.
      
      * tag 'imx-soc-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (44 commits)
        ARM: imx: imx7d requires anatop
        clocksource: timer-imx-gpt: remove include of <asm/mach/time.h>
        ARM: imx: move timer driver into drivers/clocksource
        ARM: imx: remove platform headers from timer driver
        ARM: imx: provide gpt device specific irq functions
        ARM: imx: get rid of variable timer_base
        ARM: imx: define gpt register offset per device type
        ARM: imx: move clock event variables into imx_timer
        ARM: imx: set up .set_next_event hook via imx_gpt_data
        ARM: imx: setup tctl register in device specific function
        ARM: imx: initialize gpt device type for DT boot
        ARM: imx: define an enum for gpt timer device type
        ARM: imx: move timer resources into a structure
        ARM: imx: use relaxed IO accessor in timer driver
        ARM: imx: make imx51/3 suspend optional
        ARM: clk-imx6q: refine sata's parent
        ARM: imx: clk-v610: Add clock for I2C2 and I2C3
        ARM: mach-imx: iomux-imx31: Use DECLARE_BITMAP
        ARM: imx: add imx7d clk tree support
        ARM: clk: imx: update pllv3 to support imx7
        ...
      
       Conflicts:
      	arch/arm/mach-imx/Kconfig
      3e0d0b81
    • Kevin Hilman's avatar
      Merge branch 'socfpga/soc' into next/soc · 2f69b1a4
      Kevin Hilman authored
      * socfpga/soc:
        ARM: socfpga: support suspend to ram
        ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
        ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
      2f69b1a4
    • Alan Tull's avatar
      ARM: socfpga: support suspend to ram · 44fd8c7d
      Alan Tull authored
      Add code that requests that the sdr controller go into
      self-refresh mode.  This code is run from ocram.
      
      Suspend-to-RAM and EDAC support are mutually exclusive on
      SOCFPGA.  If the EDAC is enabled, it will prevent the
      platform from going into suspend.
      
      Example of how to request to suspend to ram:
       $ echo enabled > \
      /sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup
      
       $ echo -n mem > /sys/power/state
      Signed-off-by: default avatarAlan Tull <atull@opensource.altera.com>
      Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
      Signed-off-by: default avatarKevin Hilman <khilman@linaro.org>
      44fd8c7d
    • Dinh Nguyen's avatar
      ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 · 45be0cdb
      Dinh Nguyen authored
      Add boot_secondary implementation for the Arria10 platform. Bringing up
      the secondary core on the Arria 10 platform is pretty similar to the
      Cyclone/Arria 5 platform, with the exception of the following differences:
      
      - Register offset to bringup CPU1 out of reset is different.
      - The cpu1-start-addr for Arria10 contains an additional nibble.
      Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
      Signed-off-by: default avatarKevin Hilman <khilman@linaro.org>
      45be0cdb
    • Dinh Nguyen's avatar
      ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5 · 5f763ef8
      Dinh Nguyen authored
      Convert cyclone5/arria5 to use CPU_METHOD_OF_DECLARE for smp operations.
      Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
      Signed-off-by: default avatarKevin Hilman <khilman@linaro.org>
      5f763ef8
  3. 05 Jun, 2015 15 commits
  4. 03 Jun, 2015 7 commits