- 18 Jul, 2023 5 commits
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Alex Deucher authored
Use current uclk to be consistent with other dGPUs. Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Use average gfxclock for consistency with other dGPUs. Reviewed-by:
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Joshua Ashton authored
Steam Deck/Gamescope wants to take advantage of more planes which is possible on VanGogh but was not previously exposed. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Melissa Wen <mwen@igalia.com> Cc: Simon Ser <contact@emersion.fr> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Joshua Ashton <joshua@froggi.es> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Joshua Ashton authored
DCN planes are universal and therefore overlay planes can use the same formats as primary planes, unlike DCE. Gamescope/Steam Deck would like to take advantage of this functionality for partial composition which in some cases in our pipeline, can contain negative values in some instances. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Melissa Wen <mwen@igalia.com> Cc: Simon Ser <contact@emersion.fr> Reviewed-by:
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Saleemkhan Jamadar authored
VCN FW depncencies revert it to unblock others This reverts commit f3fa86f5. Signed-off-by:
Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Acked-by:
Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Signed-off-by:
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- 13 Jul, 2023 6 commits
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Saleemkhan Jamadar authored
VCN FW depncencies revert it to unlock others This reverts commit 3ebfa943. Signed-off-by:
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Guchun Chen authored
In below thousands of screen rotation loop tests with virtual display enabled, a CPU hard lockup issue may happen, leading system to unresponsive and crash. do { xrandr --output Virtual --rotate inverted xrandr --output Virtual --rotate right xrandr --output Virtual --rotate left xrandr --output Virtual --rotate normal } while (1); NMI watchdog: Watchdog detected hard LOCKUP on cpu 1 ? hrtimer_run_softirq+0x140/0x140 ? store_vblank+0xe0/0xe0 [drm] hrtimer_cancel+0x15/0x30 amdgpu_vkms_disable_vblank+0x15/0x30 [amdgpu] drm_vblank_disable_and_save+0x185/0x1f0 [drm] drm_crtc_vblank_off+0x159/0x4c0 [drm] ? record_print_text.cold+0x11/0x11 ? wait_for_completion_timeout+0x232/0x280 ? drm_crtc_wait_one_vblank+0x40/0x40 [drm] ? bit_wait_io_timeout+0xe0/0xe0 ? wait_for_completion_interruptible+0x1d7/0x320 ? mutex_unlock+0x81/0xd0 amdgpu_vkms_crtc_atomic_disable It's caused by a stuck in lock dependency in such scenario on different CPUs. CPU1 CPU2 drm_crtc_vblank_off hrtimer_interrupt grab event_lock (irq disabled) __hrtimer_run_queues grab vbl_lock/vblank_time_block amdgpu_vkms_vblank_simulate amdgpu_vkms_disable_vblank drm_handle_vblank hrtimer_cancel grab dev->event_lock So CPU1 stucks in hrtimer_cancel as timer callback is running endless on current clock base, as that timer queue on CPU2 has no chance to finish it because of failing to hold the lock. So NMI watchdog will throw the errors after its threshold, and all later CPUs are impacted/blocked. So use hrtimer_try_to_cancel to fix this, as disable_vblank callback does not need to wait the handler to finish. And also it's not necessary to check the return value of hrtimer_try_to_cancel, because even if it's -1 which means current timer callback is running, it will be reprogrammed in hrtimer_start with calling enable_vblank to make it works. v2: only re-arm timer when vblank is enabled (Christian) and add a Fixes tag as well v3: drop warn printing (Christian) v4: drop superfluous check of blank->enabled in timer function, as it's guaranteed in drm_handle_vblank (Christian) Fixes: 84ec374b ("drm/amdgpu: create amdgpu_vkms (v4)") Cc: stable@vger.kernel.org Suggested-by:Christian König <christian.koenig@amd.com> Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Aurabindo Pillai authored
[Why&How] DCN301 does not have FAMS hence the workaround needed on other DCN3x variants related to OTG min/max selector programming is not applicable for it. Hence isolate it and have it use the old sequence without workaround. Fixes: 1598fc57 ("drm/amd/display: Program OTG vtotal min/max selectors unconditionally for DCN1+") Reviewed-by:
Swapnil Patel <swapnil.patel@amd.com> Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Make a few functions non static so that they can be reused for other asic. This is in preparation for separating out OTG programming sequence for DCN301 Fixes: 1598fc57 ("drm/amd/display: Program OTG vtotal min/max selectors unconditionally for DCN1+") Reviewed-by:
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Mario Limonciello authored
SMU7 does a check if the dGPU is inserted into a Rocket Lake system, to turn off DPM. Extend this check to all systems that have problems with dynamic switching by using the amdgpu_device_pcie_dynamic_switching_supported() helper. Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fix below checkpatch error & warnings: ERROR: trailing statements should be on next line + default: BUG(); WARNING: braces {} are not necessary for single statement blocks WARNING: braces {} are not necessary for any arm of this statement WARNING: Block comments should align the * on each line Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Acked-by:
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- 12 Jul, 2023 28 commits
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Randy Dunlap authored
Quash 175 kernel-doc warnings in dc.h by unmarking 2 struct comments as containing kernel-doc notation and by spelling one struct field correctly in a kernel-doc comment. Fixes: 1682bd1a ("drm/amd/display: Expand kernel doc for DC") Fixes: ea76895f ("drm/amd/display: Document pipe split policy") Fixes: f6ae69f4 ("drm/amd/display: Include surface of unaffected streams") Reviewed-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
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Luben Tuikov authored
Rename struct amdgpu_vm_tlb_seq_cb {...} to struct amdgpu_vm_tlb_seq_struct {...}, so as to not conflict with documentation processing tools. Of course, C has no problem with this. Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Link: https://lore.kernel.org/r/b5ebc891-ee63-1638-0377-7b512d34b823@infradead.orgSigned-off-by:Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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Srinivasan Shanmugam authored
Dynamically allocate large local variable instead of putting it onto the stack to avoid exceeding the stack size: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c: In function ‘amdgpu_amdkfd_unmap_hiq’: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c:868:1: warning: the frame size of 1280 bytes is larger than 1024 bytes [-Wframe-larger-than=] Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202307080505.V12qS0oz-lkp@intel.comSuggested-by:
Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
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Jonathan Kim authored
The feature to save the dispatch ID in trap temporaries 6 & 7 on context save is unconditionally enabled during MQD initialization. Now that TTMPs are always setup regardless of debug mode for GC 9.4.3, we should report that the dispatch ID is always available for debug/trap handling. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Mario Limonciello authored
SMU13 overrides dynamic PCIe lane width and dynamic speed by when on certain hosts. commit 38e4ced8 ("drm/amd/pm: conditionally disable pcie lane switching for some sienna_cichlid SKUs") worked around this issue by setting up certain SKUs to set up certain limits, but the same fundamental problem with those hosts affects all SMU11 implmentations as well, so align the SMU11 and SMU13 driver handling. Signed-off-by:
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Mario Limonciello authored
This helper is used for checking if the connected host supports the feature, it can be moved into generic code to be used by other smu implementations as well. Signed-off-by:
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Saleemkhan Jamadar authored
add session context buffer to decoder ring test for vcn v1 to v3. v3 - correct the cmd for sesssion ctx buf v2 - add the buffer into IB (Leo liu) Signed-off-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Saleemkhan Jamadar authored
add session context buffer to decoder ring test. v5 - clear the session ct buffer (Christian) v4 - data type, explain change of ib size change (Christian) v3 - indent and v2 changes correction. (Christian) v2 - put the buffer at the end of the IB (Christian) Signed-off-by:
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Simon Ser authored
Up until now, amdgpu was silently degrading to vsync when user-space requested an async flip but the hardware didn't support it. The hardware doesn't support immediate flips when the update changes the FB pitch, the DCC state, the rotation, enables or disables CRTCs or planes, etc. This is reflected in the dm_crtc_state.update_type field: UPDATE_TYPE_FAST means that immediate flip is supported. Silently degrading async flips to vsync is not the expected behavior from a uAPI point-of-view. Xorg expects async flips to fail if unsupported, to be able to fall back to a blit. i915 already behaves this way. This patch aligns amdgpu with uAPI expectations and returns a failure when an async flip is not possible. Signed-off-by:
Simon Ser <contact@emersion.fr> Reviewed-by:
André Almeida <andrealmeid@igalia.com> Reviewed-by:
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Mario Limonciello authored
Intel platforms such as Sapphire Rapids and Raptor Lake don't support dynamic pcie lane or speed switching. This limitation seems to carry over from one generation to another. To be safer, disable dynamic pcie lane width and speed switching when running on an Intel platform. Link: https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/ Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2663Co-developed-by:
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Tao Zhou authored
Configure SQ watchdog timer setting. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Mukul Joshi authored
For GFX9.4.3, setup a reduced default CWSR grace period equal to 1000 cycles instead of 64000 cycles. Signed-off-by:
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Ran Sun authored
Fix five occurrences of the checkpatch.pl error: ERROR: "(foo*)" should be "(foo *)" Signed-off-by:
Ran Sun <sunran001@208suo.com> Signed-off-by:
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Ran Sun authored
Fix eleven occurrences of the checkpatch.pl error: ERROR: that open brace { should be on the previous line Signed-off-by: -
Ran Sun authored
Fix four occurrences of the checkpatch.pl error: ERROR: "(foo*)" should be "(foo *)" Signed-off-by:
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Ran Sun authored
Fix four occurrences of the checkpatch.pl error: ERROR: "(foo*)" should be "(foo *)" Signed-off-by:
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Ran Sun authored
Fix nine occurrences of the checkpatch.pl error: ERROR: "foo * bar" should be "foo *bar" Signed-off-by:
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Lang Yu authored
Replace the old ones with psp_execute_load_ip_fw. Suggested-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
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Lang Yu authored
This will make this function more general, and then serve other IPs. Suggested-by:
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Jonathan Kim authored
Similar to GC v9.4.2, GC v9.4.3 should use the 5-Dword extended MAP_PROCESS packet to support multi-process debugging. Update the mutli-process debug support list so that the KFD updates the runlist on debug mode setting and that it allocates enough GTT memory during KFD device initialization. Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
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Jonathan Kim authored
Set watch points for all xcc instances on GFX943. Signed-off-by:
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Jonathan Kim authored
The additional information that the KFD reports to the debugger was destroyed when the following commit was merged: "drm/amdkfd: convert switches to IP version checking" Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Acked-by:
Amber Lin <amber.lin@amd.com> Signed-off-by:
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Eric Huang authored
Implement the similarities as GC v9.4.2, and the difference for GC v9.4.3 HW spec, i.e. xcc instance. Signed-off-by:
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Evan Quan authored
So that SMU13.0.0 and SMU13.0.7 do not need to have one copy each. Signed-off-by:
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Arnd Bergmann authored
On 32-bit architectures comparing a resource against a value larger than U32_MAX can cause a warning: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1344:18: error: result of comparison of constant 4294967296 with expression of type 'resource_size_t' (aka 'unsigned int') is always false [-Werror,-Wtautological-constant-out-of-range-compare] res->start > 0x100000000ull) ~~~~~~~~~~ ^ ~~~~~~~~~~~~~~ As gcc does not warn about this in dead code, add an IS_ENABLED() check at the start of the function. This will always return success but not actually resize the BAR on 32-bit architectures without high memory, which is exactly what we want here, as the driver can fall back to bank switching the VRAM access. Fixes: 31b8adab ("drm/amdgpu: require a root bus window above 4GB for BAR resize") Reviewed-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Philip Yang authored
Retry faults are delegated to soft IH ring and then processed by deferred worker. Current soft IH ring size PAGE_SIZE can store 128 entries, which may overflow and drop retry faults, causes HW stucks because the retry fault is not recovered. Increase soft IH ring size to 8KB, enough to store 256 CAM entries because we clear the CAM entry after handling the retry fault from soft ring. Define macro IH_RING_SIZE and IH_SW_RING_SIZE to remove duplicate constant. Show warning message if soft IH ring overflows with CAM enabled because this should not happen. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Alex Deucher authored
rlc_init() is part of sw_init() so it should not touch hardware. Additionally, calling the rlc update_spm_vmid() callback directly invokes a gfx on/off cycle which could result in powergating being enabled before hw init is complete. Split update_spm_vmid() into an internal implementation for local use without gfxoff interaction and then the rlc callback which includes gfxoff handling. Acked-by:
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Alex Deucher authored
rlc_init() is part of sw_init() so it should not touch hardware. Additionally, calling the rlc update_spm_vmid() callback directly invokes a gfx on/off cycle which could result in powergating being enabled before hw init is complete. Split update_spm_vmid() into an internal implementation for local use without gfxoff interaction and then the rlc callback which includes gfxoff handling. lbpw_init also touches hardware so mvoe that to rlc_resume as well. Acked-by:
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- 10 Jul, 2023 1 commit
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Srinivasan Shanmugam authored
Fix the below checkpatch errors & warnings: ERROR: that open brace { should be on the previous line ERROR: space prohibited before that ',' (ctx:WxV) ERROR: space required after that ',' (ctx:WxV) ERROR: code indent should use tabs where possible ERROR: switch and case should be at the same indent WARNING: please, no spaces at the start of a line WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: space prohibited before semicolon WARNING: Block comments use a trailing */ on a separate line WARNING: Block comments use * on subsequent lines WARNING: braces {} are not necessary for any arm of this statement WARNING: Missing a blank line after declarations Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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