- 28 May, 2015 7 commits
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Russell King authored
The drm_mm debugfs output is difficult to read as two different formats are used for the addresses: 0x00000080000000-0x0000008000b000: 45056: used 0x8000b000-0x80016000: 45056: free 0x00000080016000-0x0000008001b000: 20480: used 0x8001b000-0x817a1000: 24666112: free 0x000000817a1000-0x000000817a8000: 28672: used 0x000000817a8000-0x00000081ba8000: 4194304: used Fix this by using %#018llx for all addresses, thus making the output: 0x0000000080000000-0x000000008000b000: 45056: used 0x000000008000b000-0x0000000080016000: 45056: free 0x0000000080016000-0x000000008001b000: 20480: used 0x000000008001b000-0x00000000817a1000: 24666112: free 0x00000000817a1000-0x00000000817a8000: 28672: used 0x00000000817a8000-0x0000000081ba8000: 4194304: used Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
- cpt modeset sequence fixes from Ville - more rps boosting tuning from Chris - S3 support for skl (Damien) - a pile of w/a for bxt from various people - cleanup of primary plane pixel formats (Damien) - a big pile of small patches with fixes and cleanups all over * tag 'drm-intel-next-2015-05-22' of git://anongit.freedesktop.org/drm-intel: (90 commits) drm/i915: Update DRIVER_DATE to 20150522 drm/i915: Introduce DRM_I915_THROTTLE_JIFFIES drm/i915: Use the correct destructor for freeing requests on error drm/i915/skl: don't fail colorkey + scaler request drm/i915: Enable GTT caching on gen8 drm/i915: Move WaProgramL3SqcReg1Default:bdw to init_clock_gating() drm/i915: Use ilk_init_lp_watermarks() on BDW drm/i915: Disable FDI RX/TX before the ports drm/i915: Disable CRT port after pipe on PCH platforms drm/i915: Disable SDVO port after the pipe on PCH platforms drm/i915: Disable HDMI port after the pipe on PCH platforms drm/i915: Fix the IBX transcoder B workarounds drm/i915: Write the SDVO reg twice on IBX drm/i915: Fix DP enhanced framing for CPT drm/i915: Clean up the CPT DP .get_hw_state() port readout drm/i915: Clarfify the DP code platform checks drm/i915: Remove the double register write from intel_disable_hdmi() drm/i915: Remove a bogus 12bpc "toggle" from intel_disable_hdmi() drm/i915/skl: Deinit/init the display at suspend/resume drm/i915: Free RPS boosts for all laggards ...
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
for amdgpu separately next week. Highlights for radeon: - VCE1 support - Bug fixes and misc cleanups * 'drm-next-4.2' of git://people.freedesktop.org/~agd5f/linux: radeon: Deinline indirect register accessor functions drm/radeon: Fix max_vblank_count value for current display engines drm/radeon: stop using addr to check for BO move drm/radeon: clean up radeon_audio_enable drm/radeon: take the mode_config mutex when dealing with hpds (v2) drm/radeon: make dpcd parameters const drm/radeon: Use DECLARE_BITMAP drm/radeon/tn/si: enable/disable vce cg when encoding v2 drm/radeon: add support for vce 1.0 clock gating drm/radeon: add VCE 1.0 support v4 drm/radeon/dpm: add vce support for SI drm/radeon/dpm: add vce dpm support for TN drm/radeon: implement tn_set_vce_clocks drm/radeon: implement si_set_vce_clocks v2 drm/radeon: allow some more VCE firmware versions drm/radeon: rework VCE FW size calculation drm/radeon: add a GPU reset counter queryable by userspace
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Denys Vlasenko authored
This patch deinlines indirect register accessor functions. These functions perform two mmio accesses, framed by spin lock/unlock. Spin lock/unlock by itself takes more than 50 cycles in ideal case (if lock is exclusively cached on current CPU). With this .config: http://busybox.net/~vda/kernel_config, after uninlining these functions have sizes and callsite counts as follows: r600_uvd_ctx_rreg: 111 bytes, 4 callsites r600_uvd_ctx_wreg: 113 bytes, 5 callsites eg_pif_phy0_rreg: 106 bytes, 13 callsites eg_pif_phy0_wreg: 108 bytes, 13 callsites eg_pif_phy1_rreg: 107 bytes, 13 callsites eg_pif_phy1_wreg: 108 bytes, 13 callsites rv370_pcie_rreg: 111 bytes, 21 callsites rv370_pcie_wreg: 113 bytes, 24 callsites r600_rcu_rreg: 111 bytes, 16 callsites r600_rcu_wreg: 113 bytes, 25 callsites cik_didt_rreg: 106 bytes, 10 callsites cik_didt_wreg: 107 bytes, 10 callsites tn_smc_rreg: 106 bytes, 126 callsites tn_smc_wreg: 107 bytes, 116 callsites eg_cg_rreg: 107 bytes, 20 callsites eg_cg_wreg: 108 bytes, 52 callsites Functions r100_mm_rreg() and r100_mm_rreg() have a fast path and a locked (slow) path. This patch deinlines only slow path. r100_mm_rreg_slow: 78 bytes, 2083 callsites r100_mm_wreg_slow: 81 bytes, 3570 callsites Reduction in code size is more than 65,000 bytes: text data bss dec hex filename 85740176 22294680 20627456 128662312 7ab3b28 vmlinux.before 85674192 22294776 20627456 128598664 7aa4288 vmlinux Signed-off-by:
Denys Vlasenko <dvlasenk@redhat.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: linux-kernel@vger.kernel.org Signed-off-by:
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Michel Dänzer authored
The value was much too low, which could cause the userspace visible vblank counter to move backwards when the hardware counter wrapped around. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Christian König authored
It is theoretically possible that a swapped out BO gets the same GTT address, but different backing pages while being swapped in. Instead just use another VA state to note updated areas. Signed-off-by:
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Alex Deucher authored
- make it static - fix mask/bool handling for last param Signed-off-by:
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- 26 May, 2015 15 commits
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Alex Deucher authored
Since we are messing with state in the worker. v2: drop the changes in the mst worker Signed-off-by: -
Alex Deucher authored
Signed-off-by: -
Joe Perches authored
Use the generic mechanism to declare a bitmap instead of unsigned long. Signed-off-by:
Joe Perches <joe@perches.com> Signed-off-by:
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Alex Deucher authored
Some of the vce clocks are automatic, others need to be manually enabled. For ease, just disable cg when vce is active. v2: rebased, call vce_v1_0_enable_mgcg directly Signed-off-by:
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Alex Deucher authored
Signed-off-by: -
Christian König authored
Initial support for VCE 1.0 using newest firmware. v2: rebased v3: fix for TN v4: fix FW size calculation Signed-off-by:
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Alex Deucher authored
Signed-off-by: -
Alex Deucher authored
Signed-off-by: -
Alex Deucher authored
This implements the function to set the vce clocks on TN hardware. Signed-off-by: -
Christian König authored
For setting clocks with VCE v1.0 v2: (chk) rebased on current tree Signed-off-by:
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Christian König authored
They seem to work fine with the kernel interface. Signed-off-by:
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Christian König authored
Previously we were completely over allocating, fix this by actually implementing the size calculation. Signed-off-by:
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Marek Olšák authored
Userspace will be able to tell whether a GPU reset occured by comparing an old referece value of the counter with a new value. Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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git://linuxtv.org/pinchartl/fbdevDave Airlie authored
adv7511 fix. * 'drm/next/adv7511' of git://linuxtv.org/pinchartl/fbdev: drm: adv7511: Fix crash in IRQ handler when no encoder is associated
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git://linuxtv.org/pinchartl/fbdevDave Airlie authored
rcar-du fixes * 'drm/next/rcar-du' of git://linuxtv.org/pinchartl/fbdev: drm: rcar-du: Split planes pre-association 4/4 between CRTCs drm: rcar-du: Store the number of CRTCs per group in the group structure drm: rcar-du: Consider plane to CRTC associations in the plane allocator drm: rcar-du: Keep plane to CRTC associations when disabling a plane drm: rcar-du: Add plane allocation debugging drm: rcar-du: Rename to_rcar_du_plane_state to to_rcar_plane_state drm: rcar-du: Embed rcar_du_planes structure into rcar_du_group drm: rcar-du: Move properties from rcar_du_planes to rcar_du_device drm: rcar-du: Document the rcar_du_plane_state structure drm: rcar-du: Document the rcar_du_crtc structure
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- 25 May, 2015 11 commits
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Laurent Pinchart authored
If we have more than one CRTCs in a group pre-associate planes 0-3 with CRTC 0 and planes 4-7 with CRTC 1 to minimize flicker occurring when the association is changed. The pre-association could be controlled by a module parameter if needed. Signed-off-by:Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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Laurent Pinchart authored
The number of CRTCs in a group is only used to implement plane initialization for now, but is also needed to implement pre-association of planes to CRTCs. Store it in the group structure instead of computing it on demand. Signed-off-by: -
Laurent Pinchart authored
Hardware planes are driven by the timing generator of the CRTC they are associated to. Changing the association requires restarting the CRTC group that the plane belongs to, resulting in flicker on the other CRTC. To avoid flicker as much as possible, try to allocate planes first from the free planes already associated with the target CRTC. If allocation fails then fall back to allocation from all free planes. Signed-off-by: -
Laurent Pinchart authored
Changing the plane to CRTC associations requires restarting the CRTC group, creating visible flicker. Mitigate the issue by changing plane association only when a plane becomes enabled, not when it get disabled. Signed-off-by: -
Laurent Pinchart authored
Plane allocation is a complex process, add debugging statements to help finding out what could might wrong. Signed-off-by: -
Laurent Pinchart authored
All other cast functions are named without using "du", make the plane state cast consistent with them. Signed-off-by: -
Laurent Pinchart authored
The rcar_du_planes structure contains a single field and is only instantiated in the rcar_du_group structure. Embed it directly and remove the rcar_du_planes structure. Signed-off-by: -
Laurent Pinchart authored
The plane property objects are instantiated once per CRTC group, while they should be instantiated once globally for the device. Fix this and move them to the rcar_du_device structure. Signed-off-by: -
Laurent Pinchart authored
Document the structure fields using kerneldoc. Signed-off-by: -
Laurent Pinchart authored
Document the structure fields using kerneldoc. Signed-off-by: -
Laurent Pinchart authored
The ADV7511 is probed before its slave encoder init function associates it with an encoder. This creates a time window during which hot plug detection interrupts can occur with an encoder, resulting in a crash in the IRQ handler. Fix this by ignoring hot plug detection IRQs when no encoder is associated yet. Signed-off-by:
Lars-Peter Clausen <lars@metafoo.de>
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- 22 May, 2015 7 commits
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Daniel Vetter authored
Signed-off-by:Daniel Vetter <daniel.vetter@ffwll.ch>
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Chris Wilson authored
As Daniel commented on commit b7ffe1362c5f468b853223acc9268804aa92afc8 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Mon Apr 27 13:41:24 2015 +0100 drm/i915: Free RPS boosts for all laggards it is better to be explicit when sharing hardcoded values such as throttle/boost timeouts. Make it so! Signed-off-by:Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Chris Wilson authored
After allocating from the slab cache, we then need to free the request back into the slab cache upon error (and not call kfree as that leads to eventual memory corruption). Fixes regression from commit efab6d8d Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Tue Apr 7 16:20:57 2015 +0100 drm/i915: Use a separate slab for requests Signed-off-by:
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Chandra Konduru authored
There is a mplayer video failure reported with xv. This is because there is a request to do both plane scaling and colorkey. Because skl hw doesn't support plane scaling and colorkey at the same time, request is failed which is expected behavior. To make xv operate, this patch allows colorkey continue to work without using scaler. Then behavior would be similar to platforms without plane scaler support. Signed-off-by:
Chandra Konduru <chandra.konduru@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90449 [danvet: change can_scale to bool as requested by Ville.] Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Ville Syrjälä authored
GTT caching was disabled by default on gen8 due to not working with big pages. Some information suggests that it got fixed, but still GTT caching has been left disabled by default. Or could be it just meant that the default was changed to off, and hence the problem got solved. Enable GTT caching in the hopes of some performance increase. Whether or not the big pages issue has been fixed is irrelevant at this stage since we don't use big pages. This gives me a 1-2% improvement in xonotic on my BSW. Haven't tried BDW, but supposedly it has larger TLBs so might not benefit as much. On HSW GTT caching is enabled by default. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Ville Syrjälä authored
GEN8_L3SQCREG1 isn't saved in the context (verified by going through a context dump), and so we shouldn't be using the ring w/a code to initialize it. Also Bspec explicitly talks about MMIO and writing it with the CPU. Additionally there's another w/a WaTempDisableDOPClkGating:bdw which tells us to disable DOP clock gating around the GEN8_L3SQCREG1 write to make sure everyone notices the change. So let's do that as well. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ville Syrjälä authored
We're not using ilk_init_lp_watermarks() on BDW for some reason. Probably due to the BDW patches and the relevant WM patches landing roughlly at the same time. Fix it up. Signed-off-by:
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