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- 30 Aug, 2017 1 commit
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yangbo lu authored
eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1 register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1) for eSDHC. Signed-off-by:
Yangbo Lu <yangbo.lu@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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- 28 Apr, 2017 2 commits
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yangbo lu authored
The ls1046a datasheet specified that the max SD clock frequency for eSDHC SDR104/HS200 was 167MHz, and the ls1012a datasheet specified it's 125MHz for ls1012a. So this patch is to add the limitation. Signed-off-by:
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yangbo lu authored
The loop to poll ESDHC_CLOCK_STABLE bit with mdelay would waste time because the time to stabilize is much less than 1 ms. This patch is to use udelay instead to avoid time wasting. Signed-off-by:
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- 24 Apr, 2017 5 commits
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yangbo lu authored
It's observed that eSDHC needed delay between tuning cycles for HS200 successful tuning. This patch is to set 1ms delay for that. Signed-off-by:
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yangbo lu authored
eSDHC uses tuning block for tuning procedure. So the tuning block control register must be configured properly before tuning. Signed-off-by:
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yangbo lu authored
eSDHC supports signal voltage switch from 3.3v to 1.8v by eSDHC_PROCTL[VOLT_SEL] bit. This bit changes the value of output signal SDHC_VS, and there must be a control circuit out of eSDHC to change the signal voltage according to SDHC_VS output signal. Signed-off-by:
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yangbo lu authored
eSDHC could select peripheral clock or platform clock as clock source by the PCS bit of eSDHC Control Register, and this bit couldn't be reset by software reset for all. In default, the platform clock is used. But we have to use peripheral clock since it has a higher frequency to support eMMC HS200 mode and SD UHS-I mode. This patch is to add peripheral clock support and use it instead of platform clock if it's declared in eSDHC dts node. Signed-off-by:
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Adrian Hunter authored
Devices might save and restore tuning values so that re-tuning might not be needed after a pm transition. Let drivers decide by pushing the mmc_retune_needed() logic down to them. Signed-off-by:
Ludovic Desroches <ludovic.desroches@microchip.com>
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- 13 Feb, 2017 2 commits
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yangbo lu authored
The eSDHC_PRSSTAT[SDSTB] bit indicates whether the internal card clock is stable. This bit is for the host driver to poll clock status when changing the clock frequency. It is recommended to clear eSDHC_SYSCTL[SDCLKEN] to remove glitch on the card clock when the frequency is changing. This patch is to disable SDCLKEN bit before changing frequency and enable it after SDSTB bit is set. Signed-off-by:
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yangbo lu authored
Initially all QorIQ platforms were PowerPC architecture and they didn't support card detection except several platforms. The driver added the quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION as default and this made broken-cd property in dts node didn't work. Now QorIQ platform turns to ARM architecture and most of them could support card detection. However it's a large number of dts trees that need to be fixed with broken-cd if we remove the default SDHCI_QUIRK_BROKEN_CARD_DETECTION in driver. And the users don't want to see this. So this patch is to remove this default quirk just for ARM and keep it for PowerPC.(Note, QorIQ PowerPC platform only has big-endian eSDHC while QorIQ ARM platform has big-endian or little-endian eSDHC) This makes broken-cd property work again for ARM. Signed-off-by:
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- 29 Nov, 2016 1 commit
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yangbo lu authored
The eSDHC of T4240-R1.0-R2.0 has incorrect vender version and spec version. Acturally the right version numbers should be VVN=0x13 and SVN = 0x1. This patch adds the GUTS driver support for eSDHC driver to match SoC. And fix host version to avoid that incorrect version numbers break down the ADMA data transfer. Signed-off-by:
Scott Wood <oss@buserror.net> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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- 18 Nov, 2016 1 commit
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Michael Walle authored
Since commit 87a18a6a ("mmc: mmc: Use ->card_busy() to detect busy cards in __mmc_switch()") the ESDHC driver is broken: mmc0: Card stuck in programming state! __mmc_switch mmc0: error -110 whilst initialising MMC card Since this commit __mmc_switch() uses ->card_busy(), which is sdhci_card_busy() for the esdhc driver. sdhci_card_busy() uses the PRESENT_STATE register, specifically the DAT0 signal level bit. But the ESDHC uses a non-conformant PRESENT_STATE register, thus a read fixup is required to make the driver work again. Signed-off-by:
Michael Walle <michael@walle.cc> Fixes: 87a18a6a ("mmc: mmc: Use ->card_busy() to detect busy cards in __mmc_switch()") Acked-by:
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- 26 Sep, 2016 1 commit
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Julia Lawall authored
Use of_property_read_bool to check for the existence of a property. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression e1,e2; statement S2,S1; @@ - if (of_get_property(e1,e2,NULL)) + if (of_property_read_bool(e1,e2)) S1 else S2 // </smpl> Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Acked-by:
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- 27 Jul, 2016 1 commit
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Ulf Hansson authored
Let's use the SIMPLE_DEV_PM_OPS macro when declaring/assigning the system PM callbacks, as the code gets simplified. Signed-off-by:
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- 29 Feb, 2016 1 commit
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Jisheng Zhang authored
Commit 0e748234 ("mmc: sdhci: Add size for caller in init+register") allows users of sdhci_pltfm to allocate private space in calls to sdhci_pltfm_init+sdhci_pltfm_register. This patch migrates the sdhci-of-esdhc driver to this allocation. Signed-off-by:
Jisheng Zhang <jszhang@marvell.com> Acked-by:
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- 22 Dec, 2015 1 commit
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yangbo lu authored
A previous patch had removed esdhc_of_platform_init() by mistake. static void esdhc_of_platform_init(struct sdhci_host *host) { u32 vvn; vvn = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS); vvn = (vvn & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT; if (vvn == VENDOR_V_22) host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; if (vvn > VENDOR_V_22) host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; } This patch is used to fix it by add/remove some quirks according to verdor version in probe. Signed-off-by:Yangbo Lu <yangbo.lu@freescale.com> Fixes: f4932cfd ("mmc: sdhci-of-esdhc: support both BE and LE host controller") Signed-off-by:
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- 26 Oct, 2015 4 commits
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yangbo lu authored
The eSDHC doesn't have a standard power control register, so when writing this register in stack we should do nothing to avoid incorrect operation. Signed-off-by:
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yangbo lu authored
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yangbo lu authored
To support little endian eSDHC controller, we redefine both BE and LE IO accessors. In the new accessors, use ioread*/iowrite* instead of in_be32/out_be32 and will select accessors according to endian mode in probe function. Signed-off-by:
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Yangbo Lu authored
Enable interrupt mode to detect card instead of polling mode for ls1021a by removing the quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION. This could improve data transferring performance and avoid the call trace caused by polling card status sometime. Signed-off-by:
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- 27 Aug, 2015 1 commit
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Yangbo Lu authored
For eSDHC(version < 2.3), the pre divider only could divide base clock by 2 at least. Add workaround for this to avoid unexpected issue. Signed-off-by:
Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Fixes: bd455029 ("mmc: sdhci-of-esdhc: Pre divider starts at 1") Signed-off-by:
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- 01 Jun, 2015 2 commits
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Yangbo Lu authored
Enable interrupt mode to detect card instead of polling mode for P1020/P4080/P5020/P5040/T1040 by removing the quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION. This could improve data transferring performance and avoid the call trace caused by polling card status sometime. Signed-off-by:
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Joakim Tjernlund authored
For PowerPC esdhc pre divider starts at 1, fixing the increases the actual clock from 40KHz to 50 KHz. Signed-off-by:
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- 23 Mar, 2015 1 commit
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Kevin Hao authored
In these drivers, the driver specific .remove function just a simple wrapper of function sdhci_pltfm_unregister(). So remove these wrappers and just set .remove to sdhci_pltfm_unregister(). Signed-off-by:
Kevin Hao <haokexin@gmail.com> Signed-off-by:
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- 19 Jan, 2015 2 commits
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Ulf Hansson authored
Since mmc_of_parse() may fail, let's deal with it and thus do proper error handling. Signed-off-by: -
Alessio Igor Bogani authored
The commit 0718e59a ("mmc: sdhci: move FSL ESDHC reset handling quirk into esdhc code") states that Freescale esdhc is the only controller which needs the interrupt registers restored after a reset. So it moves SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET quirk handling code into the esdhc-imx driver only. Unfortunately the same controller is used in other boards which use the of-esdhc driver instead (like powerpc P2020). Restore interrupts after reset in the sdhci-of-esdhc driver also. Signed-off-by:
Alessio Igor Bogani <alessio.bogani@elettra.eu> Signed-off-by:
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- 09 Sep, 2014 1 commit
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Peter Griffin authored
This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway. Signed-off-by:
Peter Griffin <peter.griffin@linaro.org> Signed-off-by:
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- 23 May, 2014 1 commit
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Ulf Hansson authored
The commit below introduced compile errors, let's fix them. mmc: sdhci-of-esdhc: remove platform_suspend/platform_resume callbacks Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
Chris Ball <chris@printf.net>
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- 22 May, 2014 6 commits
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Russell King authored
We don't need these hooks in order to insert code in these paths, we can just provide our own handlers and call the main sdhci handlers as appropriate. Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk> Tested-by:
Markus Pargmann <mpa@pengutronix.de> Tested-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
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Russell King authored
Add sdhci_set_uhs_signaling() and always call the set_uhs_signaling method. This avoids quirks being added into sdhci_set_uhs_signaling(). Signed-off-by:
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Russell King authored
Move the setting of mmc->actual_clock to zero into the set_clock handlers themselves. This will allow us to clean up the calling logic for the set_clock() method, and turn sdhci_set_clock() into a library function. Signed-off-by:
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Russell King authored
We don't need implementations to do this, since the only time it's necessary is when we change the clock, and the only place that happens is in sdhci_do_set_ios(). So, move it there, and remove it from the iMX platform backend. Signed-off-by:
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Russell King authored
Rather than having platform_reset_enter/platform_reset_exit methods, turn the core of the reset handling into a library function which platforms can call at the appropriate moment in their (new) reset method. Signed-off-by:
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Russell King authored
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- 27 Sep, 2013 1 commit
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Dong Aisheng authored
This enables access the actual_clock via sys. root@imx6qsabreauto:~# cat /sys/kernel/debug/mmc0/ios clock: 198000000 Hz actual clock: 198000000 Hz vdd: 17 (2.9 ~ 3.0 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 2 (4 bits) timing spec: 6 (sd uhs SDR104) signal voltage: 0 (1.80 V) Signed-off-by:
Dong Aisheng <b29396@freescale.com> Acked-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
Chris Ball <cjb@laptop.org>
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- 26 Sep, 2013 1 commit
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Dong Aisheng authored
We need a lot of imx6 specific things into common esdhc_set_clock for support SD3.0 and eMMC DDR mode which is not needed for power pc platforms, so esdhc_set_clock seems not so common anymore. Instead of keeping add platform specfics things into this common API, we choose to move that code into platform driver itself to handle. This can also exclude the dependency between imx and power pc on this headfile and is easy for maintain in the future. Signed-off-by:
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- 26 Aug, 2013 1 commit
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Haijun Zhang authored
Add suppport to get voltage from device-tree node for esdhc host, if voltage-ranges was specified in device-tree node we can get ocr_mask instead of read from host capacity register. If not voltages still can be get from host capacity register. Signed-off-by:
Haijun Zhang <haijun.zhang@freescale.com> Acked-by:
Anton Vorontsov <anton@enomsg.org> Signed-off-by:
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- 05 Jul, 2013 2 commits
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Oded Gabbay authored
The P2020 has a non-standard implementation of the SDHCI_HOST_CONTROL register. This patch adds a QUIRK in the SDHCI header to signal that a host controller has a non-standard SDHCI_HOST_CONTROL register. The patch adds a check to the function esdhc_writeb in file sdhci-of-esdhc.c, where it checks if the write is done to the SDHCI_HOST_CONTROL register and th host has the above mentioned QUIRK, then the function simply returns instead of writing to the register. The patch also detects if the processor is P2020 (by looking in dev tree) and if so, adds the QUIRK to the host->quirk2 Signed-off-by:
Oded Gabbay <ogabbay@advaoptical.com> Reviewed-by:
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Oded Gabbay authored
This patch adds support of connecting an MMC media using an 8-bit bus width connection to Freescale's P2020 H/W SDHC controller. During the probe function, the generic function mmc_of_parse is called to detect whether the controller is configured with 8-bit bus width. Also, the generic function detects if the non-removable property is set in the device tree. The function esdhc_pltfm_bus_width was added because the bus width configuration is platform specific. Signed-off-by:
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- 27 Jun, 2013 1 commit
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Lucas Stach authored
The SDCLK is divided down from the host controller clock. Host controller clock may be different from the maximum SDCLK, so get it from the platform, instead of just using the max SDCLK. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Acked-by:
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