- 24 Feb, 2021 5 commits
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c:544:34-39: WARNING: conversion to bool not needed here. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c:900:47-52: WARNING: conversion to bool not needed here. Reviewed-by:
Evan Quan <evan.quan@amd.com> Reported-by:
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Nathan Chancellor authored
Clang warns: drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:764:2: warning: variable 'structure_size' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:770:23: note: uninitialized use occurs here memset(header, 0xFF, structure_size); ^~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:753:25: note: initialize the variable 'structure_size' to silence this warning uint16_t structure_size; ^ = 0 1 warning generated. Return in the default case, as the size of the header will not be known. Fixes: de4b7cd8 ("drm/amd/pm/swsmu: unify the init soft gpu metrics function") Link: https://github.com/ClangBuiltLinux/linux/issues/1304Reviewed-by:Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
Nathan Chancellor <nathan@kernel.org> Signed-off-by:
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Mario Kleiner authored
Spatial dithering to 10 bpc depth was disabled for all DCE's. Testing on DCE-8.3 and DCE-11.2 did not show any obvious ill effects, but a measureable precision improvement (via colorimeter) when displaying a fp16 framebuffer to a 10 bpc DP or HDMI connected HDR-10 monitor. v2: enable it for all DCEs (Alex) Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Alex Deucher <alexdeucher@gmail.com> Reviewed-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2) Signed-off-by:
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Qingqing Zhuo authored
[Why] mutex_lock() was introduced in dm_disable_vblank(), which could be called in an IRQ context. Waiting in IRQ would cause issues like kernel lockup, etc. [How] Handle code that requires mutex lock on a different thread. v2: squash in compilation fix without CONFIG_DRM_AMD_DC_DCN (Alex) v3: squash in warning fix (Wei) Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Acked-by:
Bindu Ramamurthy <bindu.r@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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- 22 Feb, 2021 16 commits
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Aric Cyr authored
[Why] No reason to have uninitialized var at top of function [How] Move it to minimum scope where it's actuallty used Signed-off-by:
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Aric Cyr authored
[Why] There is a window of time where we optimize bandwidth due to no streams enabled will enable PSTATE changing but HUBPs are not disabled yet. This results in underflow counter increasing in some hotplug scenarios. [How] Set the optimize-bandwidth flag for later processing once all the HUBPs are properly disabled. Signed-off-by:
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Vladimir Stempen authored
[why] Vendor based fan noise improvement [how] Report timing synchronizable when DP streams time frame difference is less than 0.05 percent. Adjust DP DTOs and sync displays using MASTER_UPDATE_LOCK_DB_X_Y Signed-off-by:
Vladimir Stempen <vladimir.stempen@amd.com> Acked-by:
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Yongqiang Sun authored
[Why & How] Move dmub trace buffer to uncached memory. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Eryk Brol authored
[why] This check for ASIC revision is no longer useful and causes lightup issues after a topology change in MST DSC scenario. In this case, DSC configs should be recalculated for the new topology. This check prevented that from happening on certain ASICs that do, in fact, support DSC. [how] Change the ASIC revision to instead check if DSC is supported. Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Acked-by:
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Anthony Wang authored
[Why] Some external displays with DP can use seamless boot, but their audio endpoints are only enabled after hotplug. On boot, these displays inherit UEFI timings without properly initializing audio. [How] Enable display audio when seamless booting with an external monitor over DP. Signed-off-by:
Anthony Wang <anthony1.wang@amd.com> Acked-by:
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Anthony Wang authored
[Why] Seamless boot over DP MST is not POR, but is not explicitly disabled. [How] Add check for DP MST and return false in dc_validate_seamless_boot_timing. Signed-off-by:
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Stylon Wang authored
[Why] Debugfs entries being moved from DP/eDP only to be available on all connectors are cluttering the code. [How] Refactor the registration of these debugfs entries. Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Acked-by:
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Eric Bernstein authored
[Why] In some cases, this function is called when DIG BE is not connected to DIG FE, in which case a value of zero isn't invalid and assert should not be hit. [How] Remove assert and handle ENGINE_ID_UNKNOWN result in calling function. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Acked-by:
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Rodrigo Siqueira authored
When run igt@kms_vrr in a device that uses DCN2.1 architecture, we noticed multiple failures. Furthermore, when we tested a VRR demo, we noticed a system hang where the mouse pointer still works, but the entire system freezes; in this case, we don't see any dmesg warning or failure messages kernel. This happens due to a lack of vupdate_no_lock interrupt, making the userspace wait eternally to get the event back. For fixing this issue, we need to add the vupdate_no_lock interrupt in the interrupt list. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Nirmoy Das authored
Fixes: 62914a99 ("drm/amdgpu: Use mmu_interval_insert instead of hmm_mirror") Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Felix Kuehling authored
If init_cwsr_apu fails, we currently leave the kfd_process structure in place anyway. The next kfd_open will then succeed, using the existing kfd_process structure. Fix that by cleaning up the kfd_process after a failure in init_cwsr_apu. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Philip Yang <philip.yang@amd.com> Signed-off-by:
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Felix Kuehling authored
We use mmu_notifier_put to free the MMU notifier. That needs to be paired with mmu_notifier_get to work correctly. Othewrise the next patch would cause a kernel oops. Signed-off-by:
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Anson Jacob authored
This reverts commit 8866a67a. Reason for revert: This breaks hotplug of HDMI on some systems, resulting in a blank screen. Caused general hangs on boot/hotplugs. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1487 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1492 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211649Signed-off-by:
Anson Jacob <Anson.Jacob@amd.com> Reviewed-by:
Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Acked-by:
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- 18 Feb, 2021 19 commits
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Yang Li authored
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:8142:16-21: WARNING: conversion to bool not needed here Reported-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Huang Rui authored
We should commit the value after restore them back to default as well. $ echo "r" > pp_od_clk_voltage $ echo "c" > pp_od_clk_voltage Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Aurabindo Pillai authored
New proposed sequence for HUBP blanking causes regressions where the hardware would fail to enter blank which triggers an assert in the new sequence. This change brings back the old sequence. Fixes: 985faf2c ("drm/amd/display: New sequence for HUBP blank") Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Nirmoy Das authored
Mark amdgpu_ras_debugfs_create_ctrl_node() as static. Fixes: eb14235668777b ("drm/amdgpu: do not keep debugfs dentry") Reported-by:kernel test robot <lkp@intel.com> Reviewed-by:
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Aric Cyr authored
DC version 3.2.123 brings improvements in multiple areas. In summary, we highlight: - Firmware release 0.0.52 - Bug fixes on MPC OGAM sequence, display experience, etc. - Improvements on timing, transmitter control, etc. Signed-off-by:
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Anthony Koo authored
[How] Add new aux cmd fields for acquire and release Signed-off-by:
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Eric Bernstein authored
[Why] Moving definition of transmitter control from atomfirmware to internal header. [How] Update the command table code to call 1.7 and make it the default fallback path. Signed-off-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Chris Park authored
[Why] Simplify AVMUTE logic in coding [How] Avoid multiple calls on TMDS AVMUTE as updated logic now demands it. Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Sung Lee authored
[Why] With certain fclock overclocks, state 1 may be chosen as the closest clock level. This may result in this state being empty if not populated beforehand, resulting in black screens and screen corruption. [How] Copy over all soc states to clock_limits before bounding box creation to avoid any cases with empty states. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Reviewed-by:
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Stylon Wang authored
[Why] Add necessary support for Freesync HDMI in Linux DM [How] - Support Freesync HDMI by calling DC interace - Report Freesync capability to vrr_range debugfs from DRM - Depends on coming DMCU/DMUB firmware to enable feature Signed-off-by:
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Sung Lee authored
[Why] If system is overclocked, only 1 bounding box state will be sent by SMU. This results in an empty state being copied for DML calculations causing black screens and corruption. [How] Fully populate bounding box before duplicating last state. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Color corruption can occur on bootup into a login manager that applies a non-linear gamma LUT because the LUT may not actually be powered on before writing. It's cleared on the next full pipe reprogramming as we switch to LUTB from LUTA and the pipe accessing the LUT has taken it out of light sleep mode. [How] The MPCC_OGAM_MEM_PWR_FORCE register does not force the current power mode when set to 0. It only forces when set light sleep, deep sleep or shutdown. The register to actually force power on and ignore sleep modes is MPCC_OGAM_MEM_PWR_DIS - a value of 0 will enable power requests and a value of 1 will disable them. When PWR_FORCE!=0 is combined with PWR_DIS=0 then MPCC OGAM memory is forced into the state specified by the force bits. If PWR_FORCE is 0 then it respects the mode specified by MPCC_OGAM_MEM_LOW_PWR_MODE if the RAM LUT is not in use. We set that bit to shutdown on low power, but otherwise it inherits from bootup defaults. So for the fix: 1. Update the sequence to "force" power on when needed We can use MPCC_OGAM_MEM_PWR_DIS for this to turn on the memory even when the block is in bypass and pending to be enabled for the next frame. We need this for both low power enabled or disabled. If we don't set this then we can run into issues when we first program the LUT from bootup. 2. Don't apply FORCE_SEL Once we enable power requests with DIS=0 we run into the issue of the RAM being forced into light sleep and being unusable for display output. Leave this 0 like we used to for DCN20. 3. Rely on MPCC OGAM init to determine light sleep/deep sleep MPC low power debug mode isn't enabled on any ASIC currently but we'll respect the setting determined during init if it is. Lightly tested as working with IGT tests and desktop color adjustment. 4. Change the MPC resource default for DCN30 It was interleaving the dcn20 and dcn30 versions before depending on the sequence. 5. REG_WAIT for it to be on whenever we're powering up the memory Otherwise we can write register values too early and we'll get corruption. Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] We added these in DMCUB for runtime feature detection but we didn't have helpers to call these with DC error handling/logging. [How] Add helpers. Signed-off-by:
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Martin Leung authored
[Why] Hardware team remeasured, need to update timings to increase latency slightly and avoid intermittent underflows. [How] sr exit latency update. Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
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Wesley Chalmers authored
This reverts commit fd1c85d3 [Why] We are not implementing the planned new HW sequence to disable HUBP. [How] Revert most related changes to minimize possibility of regression. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
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Wesley Chalmers authored
This reverts commit f8e792dc [Why] We are not implementing the planned new HW sequence for HUBP disable. [How] Revert most related changes to minimize regressions. Signed-off-by:
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Lewis Huang authored
[Why] In following sequence driver will add counter twice on same edp stream. 1. Boot into OS. 2. Set timing with edp only. 3. Set timing with edp and external monitor. 4. Set visibility on for edp. Step 2 and 3 will add seamless boot counter twice and subtract it once in step 4. [How] Remove global counter and calculate it is used. Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
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Po-Ting Chen authored
[Why] To get the pixel statistics on every frame, change ABM sample rate from 2 to 1. [How] Change LS, HS and BL sample rate to 1. Signed-off-by:
Po-Ting Chen <robin.chen@amd.com> Reviewed-by:
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Nirmoy Das authored
Use debugfs API directly instead of drm middle layer. v2: squash in build fix (Alex) Signed-off-by:
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