1. 03 May, 2023 3 commits
  2. 25 Apr, 2023 6 commits
    • Stephen Boyd's avatar
      Merge branch 'clk-imx' into clk-next · a9863979
      Stephen Boyd authored
      * clk-imx: (25 commits)
        clk: imx: imx8ulp: update clk flag for system critical clock
        clk: imx: imx8ulp: Add tpm5 clock as critical gate clock
        clk: imx: imx8ulp: keep MU0_B clock enabled always
        clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate
        clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parents
        clk: imx: imx93: Add nic and A55 clk
        dt-bindings: clock: imx93: add NIC, A55 and ARM PLL CLK
        clk: imx: imx93: add mcore_booted module paratemter
        clk: imx: fracn-gppll: Add 300MHz freq support for imx9
        clk: imx: fracn-gppll: support integer pll
        clk: imx: fracn-gppll: disable hardware select control
        clk: imx: fracn-gppll: fix the rate table
        clk: imx: imx8mp: change the 'nand_usdhc_bus' clock to non-critical
        clk: imx: imx8mp: Add LDB root clock
        dt-bindings: clock: imx8mp: Add LDB clock entry
        clk: imx: imx8mp: correct DISP2 pixel clock type
        clk: imx: drop duplicated macro
        clk: imx: clk-gpr-mux: Provide clock name in error message
        clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate
        clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate
        ...
      a9863979
    • Stephen Boyd's avatar
      Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into clk-next · c19c6c7b
      Stephen Boyd authored
      * clk-of:
        clk: add missing of_node_put() in "assigned-clocks" property parsing
      
      * clk-samsung:
        clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical
        clk: samsung: Convert to platform remove callback returning void
        clk: samsung: exynos5433: Extract PM support to common ARM64 layer
        clk: samsung: Extract parent clock enabling to common function
        clk: samsung: Extract clocks registration to common function
        clk: samsung: exynos850: Add AUD and HSI main gate clocks
        clk: samsung: exynos850: Implement CMU_G3D domain
        clk: samsung: clk-pll: Implement pll0818x PLL type
        clk: samsung: Set dev in samsung_clk_init()
        clk: samsung: Don't pass reg_base to samsung_clk_register_pll()
        clk: samsung: Remove np argument from samsung_clk_init()
        dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
        dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
      
      * clk-rockchip:
        clk: rockchip: rk3588: make gate linked clocks critical
        clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent
      
      * clk-qcom: (57 commits)
        clk: qcom: gcc-sc8280xp: Add EMAC GDSCs
        clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
        clk: qcom: add the GPUCC driver for sa8775p
        dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
        clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling
        clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc
        clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration
        dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property
        clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`
        clk: qcom: Add Global Clock Controller driver for IPQ9574
        dt-bindings: clock: Add ipq9574 clock and reset definitions
        clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value
        clk: qcom: gcc-sm6115: Mark RCGs shared where applicable
        clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset
        dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset
        clk: qcom: apss-ipq-pll: add support for IPQ5332
        dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible
        clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types
        dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match
        dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks
        ...
      c19c6c7b
    • Stephen Boyd's avatar
      Merge branches 'clk-starfive', 'clk-fractional' and 'clk-devmof' into clk-next · 1a86e99f
      Stephen Boyd authored
       - Shrink size of clk_fractional_divider a little
       - Convert various clk drivers to devm_of_clk_add_hw_provider()
      
      * clk-starfive:
        clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers
        clk: starfive: Avoid casting iomem pointers
        MAINTAINERS: generalise StarFive clk/reset entries
        reset: starfive: Add StarFive JH7110 reset driver
        clk: starfive: Add StarFive JH7110 always-on clock driver
        clk: starfive: Add StarFive JH7110 system clock driver
        reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
        reset: starfive: Rename "jh7100" to "jh71x0" for the common code
        reset: starfive: Extract the common JH71X0 reset code
        reset: starfive: Factor out common JH71X0 reset code
        reset: Create subdirectory for StarFive drivers
        reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
        clk: starfive: Rename "jh7100" to "jh71x0" for the common code
        clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
        clk: starfive: Factor out common JH7100 and JH7110 code
        clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
        dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
        dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
      
      * clk-fractional:
        clk: Remove mmask and nmask fields in struct clk_fractional_divider
        clk: rockchip: Remove values for mmask and nmask in struct clk_fractional_divider
        clk: imx: Remove values for mmask and nmask in struct clk_fractional_divider
        clk: Compute masks for fractional_divider clk when needed.
      
      * clk-devmof:
        clk: uniphier: Use managed `of_clk_add_hw_provider()`
        clk: si5351: Use managed `of_clk_add_hw_provider()`
        clk: si570: Use managed `of_clk_add_hw_provider()`
        clk: si514: Use managed `of_clk_add_hw_provider()`
        clk: lmk04832: Use managed `of_clk_add_hw_provider()`
        clk: hsdk-pll: Use managed `of_clk_add_hw_provider()`
        clk: cdce706: Use managed `of_clk_add_hw_provider()`
        clk: axs10x: Use managed `of_clk_add_hw_provider()`
        clk: axm5516: Use managed `of_clk_add_hw_provider()`
        clk: axi-clkgen: Use managed `of_clk_add_hw_provider()`
      1a86e99f
    • Stephen Boyd's avatar
      Merge branches 'clk-xilinx', 'clk-broadcom' and 'clk-platform' into clk-next · caca6ad3
      Stephen Boyd authored
       - BCM63268 timer clock and reset controller
       - Convert platform clk drivers to remove_new
      
      * clk-xilinx:
        clocking-wizard: Support higher frequency accuracy
        clk: zynqmp: pll: Remove the limit
      
      * clk-broadcom:
        clk: bcm: Add BCM63268 timer clock and reset driver
        dt-bindings: clock: Add BCM63268 timer binding
        dt-bindings: reset: add BCM63268 timer reset definitions
        dt-bindings: clk: add BCM63268 timer clock definitions
      
      * clk-platform: (25 commits)
        clk: xilinx: Convert to platform remove callback returning void
        clk: x86: Convert to platform remove callback returning void
        clk: uniphier: Convert to platform remove callback returning void
        clk: ti: Convert to platform remove callback returning void
        clk: tegra: Convert to platform remove callback returning void
        clk: stm32: Convert to platform remove callback returning void
        clk: mvebu: Convert to platform remove callback returning void
        clk: mmp: Convert to platform remove callback returning void
        clk: keystone: Convert to platform remove callback returning void
        clk: hisilicon: Convert to platform remove callback returning void
        clk: stm32mp1: Convert to platform remove callback returning void
        clk: scpi: Convert to platform remove callback returning void
        clk: s2mps11: Convert to platform remove callback returning void
        clk: pwm: Convert to platform remove callback returning void
        clk: palmas: Convert to platform remove callback returning void
        clk: hsdk-pll: Convert to platform remove callback returning void
        clk: fixed-rate: Convert to platform remove callback returning void
        clk: fixed-mmio: Convert to platform remove callback returning void
        clk: fixed-factor: Convert to platform remove callback returning void
        clk: axm5516: Convert to platform remove callback returning void
        ...
      caca6ad3
    • Stephen Boyd's avatar
      Merge branches 'clk-mediatek', 'clk-sunplus', 'clk-loongson' and 'clk-socfpga' into clk-next · 6f7478e3
      Stephen Boyd authored
       - Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and
         MT8195 SoCs
       - Converted most Mediatek clock drivers to struct platform_driver
       - MediaTek clock drivers can be built as modules
       - Mediatek MT8188 SoC clk drivers
       - Clock driver for Sunplus SP7021 SoC
       - Reimplement Loongson-1 clk driver with DT support
       - Clk driver support for Loongson-2 SoCs
       - Migrate socfpga clk driver to of_clk_add_hw_provider()
      
      * clk-mediatek: (84 commits)
        clk: mediatek: fhctl: Mark local variables static
        clk: mediatek: Use right match table, include mod_devicetable
        clk: mediatek: Add MT8188 adsp clock support
        clk: mediatek: Add MT8188 imp i2c wrapper clock support
        clk: mediatek: Add MT8188 wpesys clock support
        clk: mediatek: Add MT8188 vppsys1 clock support
        clk: mediatek: Add MT8188 vppsys0 clock support
        clk: mediatek: Add MT8188 vencsys clock support
        clk: mediatek: Add MT8188 vdosys1 clock support
        clk: mediatek: Add MT8188 vdosys0 clock support
        clk: mediatek: Add MT8188 vdecsys clock support
        clk: mediatek: Add MT8188 mfgcfg clock support
        clk: mediatek: Add MT8188 ipesys clock support
        clk: mediatek: Add MT8188 imgsys clock support
        clk: mediatek: Add MT8188 ccusys clock support
        clk: mediatek: Add MT8188 camsys clock support
        clk: mediatek: Add MT8188 infrastructure clock support
        clk: mediatek: Add MT8188 peripheral clock support
        clk: mediatek: Add MT8188 topckgen clock support
        clk: mediatek: Add MT8188 apmixedsys clock support
        ...
      
      * clk-sunplus:
        clk: Add Sunplus SP7021 clock driver
      
      * clk-loongson:
        clk: clk-loongson2: add clock controller driver support
        dt-bindings: clock: add loongson-2 boot clock index
        MAINTAINERS: remove obsolete file entry in MIPS/LOONGSON1 ARCHITECTURE
        MIPS: loongson32: Update the clock initialization
        clk: loongson1: Re-implement the clock driver
        clk: loongson1: Remove the outdated driver
        dt-bindings: clock: Add Loongson-1 clock
      
      * clk-socfpga:
        clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
        clk: socfpga: use of_clk_add_hw_provider and improve error handling
        clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
        clk: socfpga: use of_clk_add_hw_provider and improve error handling
        clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
        clk: socfpga: use of_clk_add_hw_provider and improve error handling
      6f7478e3
    • Stephen Boyd's avatar
      Merge branches 'clk-cleanup', 'clk-aspeed', 'clk-dt', 'clk-renesas' and... · 4ec6a2f9
      Stephen Boyd authored
      Merge branches 'clk-cleanup', 'clk-aspeed', 'clk-dt', 'clk-renesas' and 'clk-skyworks' into clk-next
      
       - Support for i3c clks on Aspeed ast2600 SoCs
       - Clock driver for Skyworks Si521xx I2C PCIe clock generators
      
      * clk-cleanup:
        clk: microchip: fix potential UAF in auxdev release callback
        clk: sifive: make SiFive clk drivers depend on ARCH_ symbols
        clk: stm32h7: Remove an unused field in struct stm32_fractional_divider
        clk: tegra20: fix gcc-7 constant overflow warning
        clock: milbeaut: use devm_platform_get_and_ioremap_resource()
        clk: Print an info line before disabling unused clocks
        clk: ti: Use of_address_to_resource()
        clk: remove unnecessary (void*) conversions
        clk: at91: clk-sam9x60-pll: fix return value check
        clk: visconti: remove unused visconti_pll_provider::regmap
      
      * clk-aspeed:
        dt-bindings: clock: ast2600: Expand comment on reset definitions
        clk: ast2600: Add comment about combined clock + reset handling
        dt-bindings: clock: ast2600: remove IC36 & I3C7 clock definitions
        clk: ast2600: Add full configs for I3C clocks
        dt-bindings: clock: ast2600: Add top-level I3C clock
        clk: ast2600: allow empty entries in aspeed_g6_gates
      
      * clk-dt:
        clk: mediatek: clk-pllfh: fix missing of_node_put() in fhctl_parse_dt()
        clk: Use of_property_present() for testing DT property presence
      
      * clk-renesas:
        clk: renesas: r8a77980: Add I2C5 clock
        clk: rs9: Add support for 9FGV0441
        clk: rs9: Support device specific dif bit calculation
        dt-bindings: clk: rs9: Add 9FGV0441
        clk: rs9: Check for vendor/device ID
        clk: renesas: Convert to platform remove callback returning void
        clk: renesas: r9a06g032: Improve clock tables
        clk: renesas: r9a06g032: Document structs
        clk: renesas: r9a06g032: Drop unused fields
        clk: renesas: r9a06g032: Improve readability
        clk: renesas: r8a77980: Add Z2 clock
        clk: renesas: r8a77970: Add Z2 clock
        clk: renesas: r8a77995: Fix VIN parent clock
        clk: renesas: r8a77980: Add VIN clocks
        clk: renesas: r8a779g0: Add VIN clocks
        clk: renesas: r8a779g0: Add ISPCS clocks
        clk: renesas: r8a779g0: Add CSI-2 clocks
        clk: renesas: r8a779g0: Add thermal clock
        clk: renesas: r8a779g0: Add Audio clocks
        clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H
      
      * clk-skyworks:
        clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators
        dt-bindings: clk: si521xx: Add Skyworks Si521xx I2C PCIe clock generators
      4ec6a2f9
  3. 24 Apr, 2023 2 commits
    • Stephen Boyd's avatar
      Merge tag 'qcom-clk-for-6.4' of... · ea90f303
      Stephen Boyd authored
      Merge tag 'qcom-clk-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
      
      Pull Qualcomm clk driver updates from Bjorn Andersson:
      
      New drivers for Global clock controller on SM7150, IPQ9574, MSM8917 and
      IPQ5332 are added. New GPU clock controllers for SM6115, SM6125, SM6375
      and SA8775P are added.
      
      The APSS IPQ PLL driver is refactored to support different PLL types,
      support for the Stromer Plus PLL type is added, and support for IPQ5332
      is introduced.
      
      Helpers for settings sleep, wake and retain bits of CBCR registers are
      introduced and used in some of the newly introduced GPU clock drivers.
      
      The platform_driver remove callbacks is transitioned to remove_new, as
      part of the system wide cleanup effort.
      
      In the Display clock controller for QCM2290, the MDSS_CORE reset is
      introduced and the non-existent DSI1PHY clock is removed.
      
      IPQ4019 Global clock controller is transitioned to parent_data.
      
      USB GDSCs in SM6375, MSM8996 and MSM8998 are changed to use retention as
      disabled state, to avoid collapsing them during suspend.
      The CX GDSC in the SM6375 GPU clock controller has it's disable-wait
      value corrected.
      
      QCM2290 SDCC2 src clock moves to floor_ops.
      
      The two EMAC GDSCs are added for SC8280XP.
      
      Relevant RCGs in the SM6115 Global clock controller are moved to use
      shared_ops.
      
      PCIe PIPE clock operations on SM8350 are updated, to ensure the mux is
      parked when the parent PLL is disabled.
      
      GDSCs are added to the SC7280 LPASS audio clock controller.
      
      The RPM clock controller is transitioned to use the managed version of
      of_clk_add_hw_provider().
      Missing XO clocks are added to MSM8226 and MSM8974.
      
      DeviceTree bindings are added for the various newly supported clock
      controllers, the binding for KPSS ACC and GCC drivers are converted to
      YAML and a few fixes are introduced.
      
      * tag 'qcom-clk-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (57 commits)
        clk: qcom: gcc-sc8280xp: Add EMAC GDSCs
        clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
        clk: qcom: add the GPUCC driver for sa8775p
        dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
        clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling
        clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc
        clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration
        dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property
        clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`
        clk: qcom: Add Global Clock Controller driver for IPQ9574
        dt-bindings: clock: Add ipq9574 clock and reset definitions
        clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value
        clk: qcom: gcc-sm6115: Mark RCGs shared where applicable
        clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset
        dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset
        clk: qcom: apss-ipq-pll: add support for IPQ5332
        dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible
        clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types
        dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match
        dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks
        ...
      ea90f303
    • Andrew Halaney's avatar
      32c2f2a4
  4. 18 Apr, 2023 2 commits
  5. 17 Apr, 2023 1 commit
    • Sebastian Reichel's avatar
      clk: rockchip: rk3588: make gate linked clocks critical · 64042c28
      Sebastian Reichel authored
      RK3588 has a couple of hardware blocks called Native Interface Unit
      (NIU) that gate the clocks to devices behind them. Effectively this
      means that some clocks require two parent clocks being enabled.
      Downstream implemented this by using a separate clock driver
      ("clk-link") for them, which enables the second clock using PM
      framework.
      
      In the upstream kernel we are currently missing support for the second
      parent. The information about it is in the GATE_LINK() macro as
      linkname, but that is not used. Thus the second parent clock is not
      properly enabled. So far this did not really matter, since these clocks
      are mostly required for the more advanced IP blocks, that are not yet
      supported upstream. As this is about to change we need a fix. There
      are three options available:
      
      1. Properly implement support for having two parent clocks in the
         clock framework.
      2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not
         disabled. This wastes some power, but keeps the hack contained
         within the clock driver. Going from this to the first solution
         is easy once that has been implemented.
      3. Enabling the extra clock in the consumer driver. This leaks some
         implementation details into DT.
      
      This patch implements the second option as an intermediate solution
      until the first one is available. I used an alias for CLK_IS_CRITICAL,
      so that it's easy to see which clocks are not really critical once
      the clock framework supports a better way to implement this.
      Tested-by: default avatarVincent Legoll <vincent.legoll@gmail.com>
      Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
      Link: https://lore.kernel.org/r/20230403193250.108693-2-sebastian.reichel@collabora.comSigned-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      64042c28
  6. 14 Apr, 2023 7 commits
  7. 13 Apr, 2023 2 commits
  8. 12 Apr, 2023 2 commits
    • Stephen Boyd's avatar
      Merge tag 'clk-imx-6.4' of... · 80e9552e
      Stephen Boyd authored
      Merge tag 'clk-imx-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
      
      Pull i.MX clk driver updates from Abel Vesa:
      
       - Add clock generic devm_clk_hw_register_gate_parent_data.
       - Add audiomix block control for i.MX8MP.
       - Add support for determine_rate to composite-8m.
       - Add new macro for composite-8m to allow custom flags.
       - Let the LCDIF Pixel clock of i.MX8MM and i.MX8MN set parent rate.
       - Provide clock name in error message for clk-gpr-mux on get parent
         failure.
       - Drop duplicate imx_clk_mux_flags macro.
       - Register the i.MX8MP Media Disp2 Pix clock as bus clock.
       - Add Media LDB root clock to i.MX8MP.
       - Make i.MX8MP nand_usdhc_bus clock as non-critical.
       - Fix the rate table for fracn-gppll.
       - Disable HW control for the fracn-gppll in order to be controlled by
         register write.
       - Add support for interger PLL in fracn-gppll.
       - Add mcore_booted module parameter to i.MX93 provider.
       - Add NIC, A55 and ARM PLL clocks to i.MX93.
       - Fix i.MX8ULP XBAR_DIVBUS and AD_SLOW clock parents.
       - Use "divider closest" clock type for PLL4_PFD dividers on i.MX8ULP to
         get more accurate clock rates.
       - Mark the MU0_Bi and TPM5 clocks on i.MX8ULP as critical.
       - Update some of the critical clocks flags to allow glitchless
         on-the-fly rate change.
      
      * tag 'clk-imx-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: (25 commits)
        clk: imx: imx8ulp: update clk flag for system critical clock
        clk: imx: imx8ulp: Add tpm5 clock as critical gate clock
        clk: imx: imx8ulp: keep MU0_B clock enabled always
        clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate
        clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parents
        clk: imx: imx93: Add nic and A55 clk
        dt-bindings: clock: imx93: add NIC, A55 and ARM PLL CLK
        clk: imx: imx93: add mcore_booted module paratemter
        clk: imx: fracn-gppll: Add 300MHz freq support for imx9
        clk: imx: fracn-gppll: support integer pll
        clk: imx: fracn-gppll: disable hardware select control
        clk: imx: fracn-gppll: fix the rate table
        clk: imx: imx8mp: change the 'nand_usdhc_bus' clock to non-critical
        clk: imx: imx8mp: Add LDB root clock
        dt-bindings: clock: imx8mp: Add LDB clock entry
        clk: imx: imx8mp: correct DISP2 pixel clock type
        clk: imx: drop duplicated macro
        clk: imx: clk-gpr-mux: Provide clock name in error message
        clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate
        clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate
        ...
      80e9552e
    • Lars-Peter Clausen's avatar
      clk: qcom: rpm: Use managed `of_clk_add_hw_provider()` · f1f67db9
      Lars-Peter Clausen authored
      Use the managed `devm_of_clk_add_hw_provider()` instead of
      `of_clk_add_hw_provider()`.
      
      This makes sure the provider gets automatically removed on unbind and
      allows to completely eliminate the drivers `remove()` callback.
      Signed-off-by: default avatarLars-Peter Clausen <lars@metafoo.de>
      Reviewed-by: default avatarStephen Boyd <sboyd@kernel.org>
      Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
      Link: https://lore.kernel.org/r/20230410014502.27929-7-lars@metafoo.de
      f1f67db9
  9. 10 Apr, 2023 13 commits
  10. 09 Apr, 2023 2 commits