- 11 Oct, 2019 34 commits
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Xiaodong Yan authored
[why] 1. defer delay and sw start delay has been mixed up, defer delay was programmed to AUX_SW_CONTROL:AUX_SW_START_DELAY. 2. There's no delay for defer [how] 1. Set aux sw start to 0 2. Add delay for defer scenario Signed-off-by:
Xiaodong Yan <Xiaodong.Yan@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Charlene Liu authored
[Description] use vbios message to call smu for dpm level also only program dmdata in vsyncflip as HW requirement. Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Leo Li authored
[Why] Compiling with GCC 9.1.0 gives the following warning (I have warnings-as-errors enabled): drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/core/dc.c: In function 'dc_validate_seamless_boot_timing': drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/core/dc.c:1180:8: error: 'se' may be used uninitialized in this function [-Werror=maybe-uninitialized] 1180 | if (!se->funcs->dp_get_pixel_format( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1181 | se, | ~~~ 1182 | &hw_crtc_timing.pixel_encoding, | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1183 | &hw_crtc_timing.display_color_depth)) [How] Initialize se to NULL. Signed-off-by:Leo Li <sunpeng.li@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Martin Leung authored
[why] we found using an active DP to HDMI panel that we weren't validating dp_pixel_format and hardware timing v_front_porch, causing screen to blank and/or corrupt while attempting a seamless boot. [how] added checks during dc_validate_seamless_boot_timing for these values Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Vitaly Prosyak authored
[Why & How] Dongle 0x00E04C power down all internal circuits including AUX communication preventing reading DPCD table. Encoder will skip DP RX power down on disable output to keep receiver powered all the time. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Michael Strauss authored
[WHY] Number of audio endpoints wasn't updated from dcn20's 6 when created [HOW] Changed num_audio to 4 to match the correct sbios value Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Joseph Gravenor authored
[why] dp_48m_refclk_driver_pwdn is persistent through S3 and S5. This was worked arround in SMU FW 55.21.0. Earlier FW don't have this fix so we will hang on reboot [how] add a guard for smu versions before SMU FW 55.21.0 Signed-off-by:
Joseph Gravenor <joseph.gravenor@amd.com> Signed-off-by:
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Eric Yang authored
[Why] The SMU message to enable this feature looks at argument. Previous code didn't send right argument. This change will allow the feature to be be enabled. [How] Fixed one issue where SMU message to enable the feature was sent without setting the parameter. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Signed-off-by:
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Eric Yang authored
[Why] If 48mhz refclk is turned off during PSR, we will have issue doing link training during detection. [How] Get out of PSR before detection Signed-off-by:
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Julian Parkin authored
[Why] When diags adds a DWB via a stream update, we calculate MMHUBBUB paramaters, but dc->current_state has not yet been updated when the DWB programming happens. This leads to overflow on high bandwidth tests since the incorrect MMHUBBUB arbitration parameters are programmed. [How] Pass the updated context down to the (enable|update)_writeback functions so that they can use the correct watermarks when programming MMHUBBUB. Signed-off-by:
Julian Parkin <julian.parkin@amd.com> Reviewed-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
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Wesley Chalmers authored
[WHY] dpp2_get_optimal_number_of_taps is incorrect, and dcn2 should be using dpp1_get_optimal_number_of_taps instead Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
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Sivapiriyan Kumarasamy authored
[Why] There is a bug when determining if link training should be retried when HPD is low in dp_verify_link_cap_with_retries. [How] Correctly, fail dp_verify_link_cap_with_retries without retry when HPD is low. Signed-off-by:
Sivapiriyan Kumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by:
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Josip Pavic authored
[Why] When the driver sends a pipe set command to the DMCU FW, it does not wait for the command to complete. This can lead to unpredictable behavior if, for example, the driver were to request a pipe disable to the FW via MCP, then power down some hardware before the firmware has completed processing the command. [How] Wait for the DMCU FW to finish processing set pipe commands Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Reviewed-by:
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Nikola Cornij authored
[why] Output bitrate was mistakenly left out, causing corruption on some DSC low resolution (such as 800x600) modes. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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Aric Cyr authored
[Why] Some displays rely on the SPD verticle frequency maximum value. Must round the calculated refresh rate to the nearest integer. [How] Round the nominal calculated refresh rate to the nearest whole integer. Signed-off-by:
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Joshua Aberback authored
[Why] This function was mistakenly reverted as part of a legitimate revert. The old version that was reverted to has bad logic, and is causing situations where p-state change support is being toggled when it shouldn't be, resulting in hangs. Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Lewis Huang authored
[Why] Type-c PHY config is not align with dpcd lane count. When those values didn't match, it cause driver do link training with 4 lane but phy only can output 2 lane. The link trainig always fail. [How] 1. Modify get_max_link_cap function. According DPALT_DP4 to update max lane count. 2. Add dp_mst_verify_link_cap to handle MST case because we didn't call dp_mst_verify_link_cap for MST case. Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
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Wayne Lin authored
[Why] Didn't send VSIF infopacket when it's 4k mode defined in HDMI 1.4b. For HDMI 1.4b, While displaying 4k modes, it should send VSP. [How] Call mod_build_hf_vsif_infopacket() function to build info frame and send it. Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Anthony Koo authored
Signed-off-by:
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Joshua Aberback authored
[Why] The register CM_TEST_DEBUG_DATA is used in dpp1_program_input_csc, which is called from dpp2_cnv_setup, but the shifts and masks for the fields of that register are not initialized for dcn2. This causes all reads of that register to return 0. Signed-off-by:
Jaehyun Chung <Jaehyun.Chung@amd.com> Acked-by:
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Jun Lei authored
[why] memcmp is vulnerable to regression due to dc_clocks structures not being organized properly (not "current" clock related structures being at the beginning of the structure) and causes unnecessary setting of the optimize bit [how] add a dcn sepcific comparator, implement for dcn2 Signed-off-by:
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Wayne Lin authored
[Why] The vendor specific infoframe is needed for HDMI while displaying specific modes. DC supports sending it, but we aren't currently building it [How] Add mod_build_hf_vsif_infopacket() to build the vendor specific info packet. Signed-off-by:
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Joseph Gravenor authored
[why] HPD is not suppressed when we lower clocks on renoir. B/c of this we do link training when the 48mhz refclk is off, which will cause ASIC hang. [how] Exit optimized power state for detection purpose. Signed-off-by:
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Dmytro Laktyushkin authored
Currently pipe split may steal an existing ODM pipe depending on stream sequence. This change prevents that from happening as easily. Signed-off-by:
Gary Kattan <Gary.Kattan@amd.com> Acked-by:
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Julian Parkin authored
[Why] When planes are added or removed from a stream, the change in pipe usage from dynamic MPC combine can cause a second stream using ODM combine to pick a different pipe to combine with. In this scenario, a different OPP is connected to the ODM without programming its FMT. [How] Reprogram the FMT in dcn20_program_pipe whenever a pipe is newly enabled, or when its opp changes. Signed-off-by:
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Aric Cyr authored
[Why] If VSTARTUP changes due to bandwidth requirements, we must recalculate and update VLINE2 as well for proper flip reporting. [How] After all calls to program_global_sync which reconfigures VSTARTUP, also make sure to update V_UPDATE (i.e. VLINE2 on DCNx). Signed-off-by:
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Wyatt Wood authored
[Why] A recent bug showed that logging would be useful in debugging various gamma issues. [How] Fix formatting for easier graphing. Prevent performance hit when doing diag. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] Virtual signal means there is no display attached. In this case we will assign a virtual signal type to the stream. We should only enable the front end of the stream but not the back end. [how] When stream is enabling with virtual signal type, skip backend programming. Signed-off-by:
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Wayne Lin authored
[Why] While displaying 4k modes defined in HDMI1.4b, should set VIC to 0 and use VSP HDMI_VIC to indicate the mode. [How] Use functions defined in drm to set up the VIC correspondingly. Signed-off-by:
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Robin Singh authored
[Why] To compare the crc of the framebuffer data at input of display pipeline with the crc of the otg, we need to disable pixel formatter's dynamic expansion feature during crc capture and keep it enable in the normal operation. [HOW] Expose a new interface in DM and dc for pixel formatter (fmt dynamic bitdepth expansion control). Interface control the FMT_DYNAMIC_EXP_EN bit, during crc capture keep it disabled. Signed-off-by:
Robin Singh <robin.singh@amd.com> Reviewed-by:
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Oak Zeng authored
This allows gfx cache to be probed and invalidated (for none-dirty cache lines) on a HDP write (from either another GPU or CPU). This should work only for the memory mapped as RW memory type newly added for arcturus, to achieve some cache coherence b/t multiple memory clients. Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Acked-by:
Christian Konig <christian.koenig@amd.com> Signed-off-by:
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Oak Zeng authored
Many logic in this function are HDP set up, not gart set up. Moved those logic to gmc_v9_0_hw_init. No functional change. Signed-off-by:
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Marek Olšák authored
Use asic constants. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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- 09 Oct, 2019 1 commit
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Stephen Rothwell authored
Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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- 07 Oct, 2019 5 commits
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Harish Kasiviswanathan authored
Participate in device cgroup. All kfd devices are exposed via /dev/kfd. So use /dev/dri/renderN node. Before exposing the device to a task check if it has permission to access it. If the task (based on its cgroup) can access /dev/dri/renderN then expose the device via kfd node. If the task cannot access /dev/dri/renderN then process device data (pdd) is not created. This will ensure that task cannot use the device. In sysfs topology, all device nodes are visible irrespective of the task cgroup. The sysfs node directories are created at driver load time and cannot be changed dynamically. However, access to information inside nodes is controlled based on the task's cgroup permissions. Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Harish Kasiviswanathan authored
For AMD compute (amdkfd) driver. All AMD compute devices are exported via single device node /dev/kfd. As a result devices cannot be controlled individually using device cgroup. AMD compute devices will rely on its graphics counterpart that exposes /dev/dri/renderN node for each device. For each task (based on its cgroup), KFD driver will check if /dev/dri/renderN node is accessible before exposing it. Signed-off-by:
Tejun Heo <tj@kernel.org> Acked-by:
Roman Gushchin <guro@fb.com> Signed-off-by:
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Alex Deucher authored
Add proper ifdefs around CIK code in kfd setup. Reviewed-by:
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Krzysztof Kozlowski authored
Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^ /\t/' -i */Kconfig Signed-off-by:Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
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Ori Messinger authored
The vram vendor can be found as a separate sysfs file at: /sys/class/drm/card[X]/device/mem_info_vram_vendor The vram vendor is displayed as a string value. v2: Use correct bit masking, and cache vram_vendor in gmc v3: Drop unused functions for vram width, type, and vendor Signed-off-by:
Ori Messinger <ori.messinger@amd.com> Reviewed-by:
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