1. 30 Aug, 2023 3 commits
    • Stephen Boyd's avatar
      Merge branches 'clk-imx', 'clk-samsung', 'clk-annotate', 'clk-marvell' and 'clk-lmk' into clk-next · 3462100c
      Stephen Boyd authored
       - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc
       - Remove non-OF mmp clk drivers
       - Move number of clks from DT headers to drivers
      
      * clk-imx:
        clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz
        clk: imx: pll14xx: align pdiv with reference manual
        clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op
        clk: imx25: make __mx25_clocks_init return void
        clk: imx25: print silicon revision during init
        dt-bindings: clocks: imx8mp: make sai4 a dummy clock
        clk: imx8mp: fix sai4 clock
        clk: imx: imx8ulp: update SPLL2 type
        clk: imx: pllv4: Fix SPLL2 MULT range
        clk: imx: imx8: add audio clock mux driver
        dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support
        clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource()
        clk: imx: clk-gpr-mux: Simplify .determine_rate()
        clk: imx: Add 519.75MHz frequency support for imx9 pll
        clk: imx93: Add PDM IPG clk
        dt-bindings: clock: imx93: Add PDM IPG clk
      
      * clk-samsung:
        dt-bindings: clock: samsung: remove define with number of clocks
        clk: samsung: exynoautov9: do not define number of clocks in bindings
        clk: samsung: exynos850: do not define number of clocks in bindings
        clk: samsung: exynos7885: do not define number of clocks in bindings
        clk: samsung: exynos5433: do not define number of clocks in bindings
        clk: samsung: exynos5420: do not define number of clocks in bindings
        clk: samsung: exynos5410: do not define number of clocks in bindings
        clk: samsung: exynos5260: do not define number of clocks in bindings
        clk: samsung: exynos5250: do not define number of clocks in bindings
        clk: samsung: exynos4: do not define number of clocks in bindings
        clk: samsung: exynos3250: do not define number of clocks in bindings
      
      * clk-annotate:
        clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by
        clk: Annotate struct clk_hw_onecell_data with __counted_by
      
      * clk-marvell:
        clk: pxa910: Move number of clocks to driver source
        clk: pxa1928: Move number of clocks to driver source
        clk: pxa168: Move number of clocks to driver source
        clk: mmp2: Move number of clocks to driver source
        clk: mmp: Remove old non-OF clock drivers
      
      * clk-lmk:
        clk: lmk04832: Support using PLL1_LD as SPI readback pin
        clk: lmk04832: Don't disable vco clock on probe fail
        clk: lmk04832: Set missing parent_names for output clocks
      3462100c
    • Stephen Boyd's avatar
      Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and... · 032bcf78
      Stephen Boyd authored
      Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next
      
       - Add Versa3 clk generator to support 48KHz playback/record with audio
         codec on RZ/G2L SMARC EVK
       - Introduce kstrdup_and_replace() and use it
      
      * clk-versa:
        clk: vc7: Use i2c_get_match_data() instead of device_get_match_data()
        clk: vc5: Use i2c_get_match_data() instead of device_get_match_data()
        clk: versaclock3: Switch to use i2c_driver's probe callback
        clk: Add support for versa3 clock driver
        dt-bindings: clock: Add Renesas versa3 clock generator bindings
      
      * clk-strdup:
        clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace()
        clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace()
        driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace()
        lib/string_helpers: Add kstrdup_and_replace() helper
      
      * clk-amlogic: (22 commits)
        dt-bindings: soc: amlogic: document System Control registers
        dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema
        dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema
        clk: meson: axg-audio: move bindings include to main driver
        clk: meson: meson8b: move bindings include to main driver
        clk: meson: a1: move bindings include to main driver
        clk: meson: eeclk: move bindings include to main driver
        clk: meson: aoclk: move bindings include to main driver
        dt-bindings: clk: axg-audio-clkc: expose all clock ids
        dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
        dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids
        dt-bindings: clk: meson8b-clkc: expose all clock ids
        dt-bindings: clk: g12a-aoclkc: expose all clock ids
        dt-bindings: clk: g12a-clks: expose all clock ids
        dt-bindings: clk: axg-clkc: expose all clock ids
        dt-bindings: clk: gxbb-clkc: expose all clock ids
        clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS
        clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS
        clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
        clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS
        ...
      
      * clk-allwinner:
        clk: sunxi-ng: nkm: Prefer current parent rate
        clk: sunxi-ng: a64: select closest rate for pll-video0
        clk: sunxi-ng: div: Support finding closest rate
        clk: sunxi-ng: mux: Support finding closest rate
        clk: sunxi-ng: nkm: Support finding closest rate
        clk: sunxi-ng: nm: Support finding closest rate
        clk: sunxi-ng: Add helper function to find closest rate
        clk: sunxi-ng: Add feature to find closest rate
        clk: sunxi-ng: a64: allow pll-mipi to set parent's rate
        clk: sunxi-ng: nkm: consider alternative parent rates when determining rate
        clk: sunxi-ng: nkm: Use correct parameter name for parent HW
        clk: sunxi-ng: Modify mismatched function name
        clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource()
      
      * clk-rockchip:
        clk: rockchip: rv1126: Add PD_VO clock tree
        clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
        clk: rockchip: rk3568: Add PLL rate for 101MHz
      032bcf78
    • Stephen Boyd's avatar
      Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and... · d10ebc7c
      Stephen Boyd authored
      Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next
      
       - Remove OXNAS clk driver
      
      * clk-bindings:
        dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml
        dt-bindings: clock: xlnx,versal-clk: drop select:false
        dt-bindings: clock: versal: Add versal-net compatible string
        dt-bindings: clock: ast2600: Add I3C and MAC reset definitions
        dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding
      
      * clk-starfive:
        reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support
        clk: starfive: Simplify .determine_rate()
        clk: starfive: Add StarFive JH7110 Video-Output clock driver
        clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver
        clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
        clk: starfive: jh7110-sys: Add PLL clocks source from DTS
        clk: starfive: Add StarFive JH7110 PLL clock driver
        dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
        dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
        dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
        dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
        dt-bindings: soc: starfive: Add StarFive syscon module
        dt-bindings: clock: Add StarFive JH7110 PLL clock generator
      
      * clk-rm:
        dt-bindings: clk: oxnas: remove obsolete bindings
        clk: oxnas: remove obsolete clock driver
      
      * clk-renesas:
        clk: renesas: rcar-gen3: Add ADG clocks
        clk: renesas: r8a77965: Add 3DGE and ZG support
        clk: renesas: r8a7796: Add 3DGE and ZG support
        clk: renesas: r8a7795: Add 3DGE and ZG support
        clk: renesas: emev2: Remove obsolete clkdev registration
        clk: renesas: r9a07g043: Add MTU3a clock and reset entry
        clk: renesas: rzg2l: Simplify .determine_rate()
        clk: renesas: r9a09g011: Add CSI related clocks
        clk: renesas: r8a774b1: Add 3DGE and ZG support
        clk: renesas: r8a774e1: Add 3DGE and ZG support
        clk: renesas: r8a774a1: Add 3DGE and ZG support
        clk: renesas: rcar-gen3: Add support for ZG clock
      
      * clk-cleanup:
        clk: mvebu: Convert to devm_platform_ioremap_resource()
        clk: nuvoton: Convert to devm_platform_ioremap_resource()
        clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()
        clk: ti: Use devm_platform_get_and_ioremap_resource()
        clk: mediatek: Convert to devm_platform_ioremap_resource()
        clk: hsdk-pll: Convert to devm_platform_ioremap_resource()
        clk: gemini: Convert to devm_platform_ioremap_resource()
        clk: fsl-sai: Convert to devm_platform_ioremap_resource()
        clk: bm1880: Convert to devm_platform_ioremap_resource()
        clk: axm5516: Convert to devm_platform_ioremap_resource()
        clk: actions: Convert to devm_platform_ioremap_resource()
        clk: cdce925: Remove redundant of_match_ptr()
        drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init()
        clk: Explicitly include correct DT includes
      d10ebc7c
  2. 23 Aug, 2023 3 commits
  3. 22 Aug, 2023 25 commits
  4. 15 Aug, 2023 9 commits