- 10 Aug, 2022 40 commits
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Joseph Greathouse authored
Enable translate_further on Arcturus and Aldebaran server chips in order to increase the UTCL2 reach from 8 GiB to 64 GiB, which is more in line with the amount of framebuffer DRAM in the devices. Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Kent Russell <kent.russell@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Move fpu file to dml folder - Fix CAB allocation for multiple displays - Add a variable to update FCLK - Fix TMDS 4K@60Hz YCbCr420 corruption issue - Fix MPC tree infinite loop in some case - Fix HDMI VSIF V3 blank screen issue - Add some documentation to the code - Allow alternate prefetch modes in DML for DCN32 - Fix VPG instancing for dcn314 HPO - Check correct bounds for stream encoder instances for DCN303 - Enable SubVP by default on DCN32 & DCN321 - Fix DTBCLK not correct for dcn314 - Fix Compile-time warning - Fix the stereo mode hang issue - Fix display light up issue Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] SUBVP_START_LINE must be aligned to 2 swaths, so add 16 lines of margin so the start line can be adjusted by up to 16 lines for alignment purposes in FW. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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Meenakshikumar Somasundaram authored
[Why] After TDR recovery, eDP and USB4 display does not light up. Because dmub outbox notifications are not enabled after dmub reload and link encoder assignments for the streams are not cleared before dc state reset. [How] - Dmub outbox notification is enabled after tdr recovery by issuing inbox command to dmub. - Link encoders for the streams are unassigned before dc state reset. Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Fudong Wang authored
[Why] After ODM clock off, optc underflow bit will be kept there always and clear not work. We need to clear that before clock off. [How] Clear that if have when clock off. Reviewed-by:
Fudong Wang <Fudong.Wang@amd.com> Tested-by:
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Alvin Lee authored
[Description] MALL not supported with stereo3D according to DCN doc. Reviewed-by:
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Alvin Lee authored
[Description] Observed in stereomode that programming FLIP_LEFT_EYE can cause hangs. Keep FLIP_ANY_FRAME in stereo mode so the surface flip can take place before left or right eye Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Alvin Lee authored
[Description] Reverts commit "attempt to fix the logic in commit_planes_for_stream()" since it caused a regression. Reviewed-by:
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Duncan Ma authored
[Why] DTBCLK clocks reset after clocks are initialized and bounding box values are also incorrect. [How] Use dcn31 init clock function programming sequence and correct bounding box values for dcn314 Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why&How] Set the debug options to enable SubVP feature Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why & How] eng_id for DCN303 cannot be more than 1, since we have only two instances of stream encoders. Check the correct boundary condition for engine ID for DCN303 prevent the potential out of bounds access. Fixes: cd6d421e ("drm/amd/display: Initial DC support for Beige Goby") Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Cc: stable@vger.kernel.org Reviewed-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Duncan Ma authored
[Why] An issue during VPG indexing offset generation causing to use the incorrect VPG. HW team placed VPG instances 5 at end of list, making it VPG 9 in register headers. [How] Correct VPG instance for HPO encoders. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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David Galiffi authored
Fixed bracketing around condition statement. Reviewed-by:
David Galiffi <David.Galiffi@amd.com> Tested-by:
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David Galiffi authored
[Why] Driver is restricting voltage levels if system cannot switch in vblank. [How] Change allow_for_pstate_or_stutter_in_vblank_final from dm_prefetch_support_uclk_fclk_and_stutter to dm_prefetch_support_uclk_fclk_and_stutter_if_possible. Add support for a new registry property, DalDMLDisallowAlternatePrefetchModes, for easier debugging. Reviewed-by:
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Leo Ma authored
[Why] Reported from customer the checksum in AMD VSIF V3 is incorrect and causing blank screen issue. [How] Fix the packet length issue on AMD HDMI VSIF V3. Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Leo Ma <hanghong.ma@amd.com> Tested-by:
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Josip Pavic authored
[Why] In some cases MPC tree bottom pipe ends up point to itself. This causes iterating from top to bottom to hang the system in an infinite loop. [How] When looping to next MPC bottom pipe, check that the pointer is not same as current to avoid infinite loop. Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Tested-by:
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Chiawen Huang authored
[Why] Enabling stream with tg lock makes config settings pending causing the garbage until tg unlock. [How] Keep the original lock mechanism The driver doesn't lock tg if plane_state is null. Reviewed-by:
Chiawen Huang <chiawen.huang@amd.com> Tested-by:
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Daniel Miess authored
[Why] DIG_FIFO_OUTPUT_PIXEL_MODE not being set for dcn314 resulting in incorrect timing for YCbCr4:2:0 [How] Copy the implementation of set_pixels_per_cycle from dcn32 over to dcn314 Reviewed-by:
Daniel Miess <Daniel.Miess@amd.com> Tested-by:
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Alvin Lee authored
[Description] Add a variable to update FCLK latency Reviewed-by:
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Aurabindo Pillai authored
[Why & How] When multiple displays are used, the underlying framebuffers could be two separate framebuffers, or a single large framebuffer. Fix the calculation logic for CAB to account for large framebuffer. Current logic assumes that any FB that the plane points to are independent. When a single FB is used on the system, this does 2 times allocation. Add a check to prevent duplicate allocation by checking if the base addresses are the same, and then ensuring that the if we allocate using the pitch, whole of the other fbs will be accounted for in the first allocation. Reviewed-by:
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Rodrigo Siqueira authored
At this point, we isolate the FPU code associated with DCN314 under the DML folder. This commit drops the FPU flags from the Makefile. Reviewed-by:
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Rodrigo Siqueira authored
The function responsible for populating DML pipes has some FPU operations, and for this reason, it must be moved to the dml folder. This commit moves such function from resource to the fpu file under the dml folder. Reviewed-by:
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Rodrigo Siqueira authored
DCN314 has multiple references to FPU operations inside the resource files, and we need to move those codes to the DML folder. This commit creates the dcn314_fpu files and moves the bounding box operation to this file. Reviewed-by:
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Daniel Miess authored
[Why] DP DSC YCbCr422 not working because dcn314_calculate_dccg_k1_k2_values does not account for two pixels per container [How] Replace the contents of dcn314_calculate_dccg_k1_k2_values with the code from the function dcn32_calculate_dccg_k1_k2_values Reviewed-by:
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Tim Huang authored
The EnableGfxOff message is dropped from the new PMFW ppsmc interface. Signed-off-by:
Tim Huang <tim.huang@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Tim Huang authored
Update the SmuMetrics_t defination and SMU driver interface version. Signed-off-by:
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Tim Huang authored
Enable GFX CG gate/ungate control. Signed-off-by:
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Tim Huang authored
Add below GFX Clock Gating supports: 1. GFX Coarse Grain Clock Gating(CGCG) 2. GFX Coarse grain light sleep/deep sleep(CGLS) 3. GFX Medium Grain Clock Gating(MGCG) 4. GFX Fine Grain Clock Gating(FGCG) 5. Repeater Fine Grain Clock Gating 6. Perfmon Clock Gating Signed-off-by:
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Yifan Zhang authored
GC version is 11.0.1 rather than 11.0.2 Signed-off-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
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Ma Jun authored
Remove redundant reference of header file dev_printk.h Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Lijo Lazar authored
A list of devices to be reset is already created in amdgpu_device_gpu_recover function. Creating another list with the same nodes is incorrect and not supported in list_head. Instead, pass the device list as part of reset context. Fixes: 9e085647 (drm/amdgpu: Refactor mode2 reset logic for v13.0.2) Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Magali Lemes authored
Add missing headers to solve the following warnings from sparse: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:656:17: warning: symbol 'ddr4_wm_table_gs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:693:17: warning: symbol 'lpddr4_wm_table_gs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:730:17: warning: symbol 'lpddr4_wm_table_with_disabled_ppt' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:767:17: warning: symbol 'ddr4_wm_table_rn' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:804:17: warning: symbol 'ddr4_1R_wm_table_rn' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:841:17: warning: symbol 'lpddr4_wm_table_rn' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.c:217:17: warning: symbol 'ddr4_wm_table' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.c:254:17: warning: symbol 'lpddr5_wm_table' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.c:53:30: warning: symbol 'dcn3_1_ip' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.c:197:30: warning: symbol 'dcn3_15_ip' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.c:293:30: warning: symbol 'dcn3_16_ip' was not declared. Should it be static? Fixes: 1a340825 ("drm/amd/display: move FPU code on dcn21 clk_mgr") Fixes: 5085e036 ("drm/amd/display: move FPU code from dcn301 clk mgr to DML folder") Fixes: 26f4712a ("drm/amd/display: move FPU related code from dcn31 to dml/dcn31 folder") Fixes: fa896297 ("drm/amd/display: move FPU related code from dcn315 to dml/dcn31 folder") Fixes: 3f8951cc ("drm/amd/display: move FPU related code from dcn316 to dml/dcn31 folder") Signed-off-by:
Magali Lemes <magalilemes00@gmail.com> Reviewed-by:
Maíra Canal <mairacanal@riseup.net> Reviewed-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Likun Gao authored
Update the vram width algorithm for vram_info v3_0 to align with the changes of latest IFWI. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Daniel Phillips authored
Separately accumulate a statistic of rounded up allocations to use to report availability, with a view to increasing the likelihood a buffer object can be successfully allocated at exactly the size reported by the availability API. Signed-off-by:
Daniel Phillips <daniel.phillips@amd.com> Reviewed-by:
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Daniel Phillips authored
Rounding up allocations in the allocation path caused test regressions, so now just round in the availability path. Signed-off-by:
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Magali Lemes authored
Since "rn_clk_mgr.h" needs ‘struct clk_mgr_internal’ which is declared in "clk_mgr_internal.h", include "clk_mgr_internal.h" in "rn_clk_mgr.h" instead of in its source file. Because of the change above, change the order of '#include "rn_clk_mgr.h"', so that the necessary structs are visible to dcn20_clk_mgr.h. Signed-off-by:
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Magali Lemes authored
As "dcn3_1_soc", "dcn3_15_soc", and "dcn3_16_soc" are not used outside of their corresponding "dcn3*_fpu.c", make them static and remove their extern declaration. Fixes: 26f4712a ("drm/amd/display: move FPU related code from dcn31 to dml/dcn31 folder") Fixes: fa896297 ("drm/amd/display: move FPU related code from dcn315 to dml/dcn31 folder") Fixes: 3f8951cc ("drm/amd/display: move FPU related code from dcn316 to dml/dcn31 folder") Signed-off-by:
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Magali Lemes authored
There are two identical CFLAGS entries for "display_mode_vba_20.o", so remove one of them. Also, as there's already an entry for "display_mode_lib.o" CFLAGS, regardless of CONFIG_DRM_AMD_DC_DCN being defined or not, remove the one entry between CONFIG_DRM_AMD_DC_DCN ifdef guards. Signed-off-by:
André Almeida <andrealmeid@igalia.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
This reverts commit bac4b41d. This commit was a part of a patchset responsible for reducing the stack size. However, after some other changes, this commit becomes unnecessary, so we are reverting it here. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by:
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Rodrigo Siqueira authored
This reverts commit c3b3f9ba. This commit was a part of a patchset responsible for reducing the stack size. However, after some other changes, this commit becomes unnecessary, so we are reverting it here. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reported-by:
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