- 15 Aug, 2022 1 commit
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Imre Deak authored
At the moment on DG2 at least loading the DMC firmware's PIPEDMC C and D programs leads to sporadic unclaimed register accesses while programming the initial state as described by the firmware's "MMIO init" table. This will also lead to later unclaimed accesses for unrelated transcoder/pipe registers backed by the pipe C and D display power wells. Disabling the PIPEDMC clock gating during initialization - similarly to Wa_16015201720 fixed this problem in my tests. While pipe A an B requires the clock gating to be disabled all the time pipe C and D requires this only while accessing the PIPEDMC registers. Bspec: 49193 References: https://gitlab.freedesktop.org/drm/intel/-/issues/6526 References: https://gitlab.freedesktop.org/drm/intel/-/issues/6308Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Arun R Murthy <arun.r.murthy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220808103054.3586074-1-imre.deak@intel.com
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- 10 Aug, 2022 4 commits
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Piotr Piórkowski authored
For proper operation of i915 we need usable PCI GTTMMADDR BAR 0 (1 for GEN2). In most cases we also need usable PCI GFXMEM BAR 2. Let's add functions to check if BARs are set, and that it have a size greater than 0. In case GTTMMADDR BAR, let's validate at the beginning of i915 initialization. For other BARs, let's validate before first use. Signed-off-by:
Piotr Piórkowski <piotr.piorkowski@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Piotr Piórkowski authored
At the moment, when we refer to some PCI BAR we use the number of this BAR in the code. The meaning of BARs between different platforms may be different. Therefore, in order to organize the code, let's start using defined names instead of numbers. v2: Add lost header in cfg_space.c Signed-off-by:
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Jani Nikula authored
Registers contents are supposed to be defined using REG_BIT() to ensure they're u32 and the shift is within bounds. Signed-off-by:
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Jani Nikula authored
Reduce the bloat of i915_reg.h. The registers are also only needed in a few places, no need to have them defined everywhere. Signed-off-by:
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- 04 Aug, 2022 1 commit
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Rodrigo Vivi authored
Sync up. In special to get the drm-intel-gt-next stuff. Signed-off-by:Rodrigo Vivi <rodrigo.vivi@intel.com>
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- 03 Aug, 2022 1 commit
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Dave Airlie authored
Merge tag 'amd-drm-next-5.20-2022-07-29' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.20-2022-07-29: amdgpu: - Misc spelling and grammar fixes - DC whitespace cleanups - ACP smatch fix - GFX 11.0 updates - PSP 13.0 updates - VCN 4.0 updates - DC FP fix for PPC64 - Misc bug fixes amdkfd: - SVM fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220729202742.6636-1-alexander.deucher@amd.com
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- 02 Aug, 2022 1 commit
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Anusha Srivatsa authored
With the latest DMC in place, enabling DC5 on DG2. Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by:
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- 29 Jul, 2022 7 commits
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Rodrigo Siqueira authored
We got a report from Stephen/Michael that the PowerPC build was failing with the following error: ld: drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o uses soft float ld: failed to merge target specific data of file drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o This error happened because of the function optc3_set_vrr_m_const. This function expects a double as a parameter in a code that is not allowed to have FPU operations. After further investigation, it became clear that optc3_set_vrr_m_const was never invoked, so we can safely drop this function and fix the ld issue. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Melissa Wen <mwen@igalia.com> Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Reported-by:
Michael Ellerman <mpe@ellerman.id.au> Tested-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Xiaojian Du authored
This patch will enable support for psp 13.0.4 blcok. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
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Xiaojian Du authored
This patch will add files for PSP 13.0.4. Signed-off-by:
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Xiaojian Du authored
This patch will add header files for MP 13.0.4. Signed-off-by:
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Yifan Zhang authored
This patch corrects RLC_RLCS_BOOTLOAD_STATUS offset and index for GC 11.0.1. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Xiaojian Du authored
This patch will make SMU send msg to IMU for the front-door loading, it is required by some ASICs. Signed-off-by:
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Yu Zhe authored
time_is_before_jiffies deals with timer wrapping correctly. Signed-off-by:
Yu Zhe <yuzhe@nfschina.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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- 28 Jul, 2022 25 commits
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Jonathan Kim authored
Hives that require psp topology info to be reflected will leak hive reference so fix it. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by:
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Evan Quan authored
The feature is ready with latest firmwares. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Evan Quan authored
And get the version bumped to 0x2C to match the latest PMFW. Signed-off-by:
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Jack Xiao authored
mes self test rely on vm mapping, move it after drm sched re-started so that vm mapping can work during gpu reset. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Acked-and-tested-by:
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Evan Quan authored
This extra call trace dump comes out in every gpu reset. And it gives people a wrong impression that something went wrong. Although actually there was not. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Sonny Jiang authored
Not enable VCN pg because encode issue Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Sonny Jiang authored
Enable support for vcn_4_0_2 video codec Signed-off-by:
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Sonny Jiang authored
Add VCN_4_0_2 firmware support Signed-off-by:
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Sonny Jiang authored
Add function to support VCN_4_0_2 doorbell Signed-off-by:
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Sonny Jiang authored
The return value should be set in vcn4 boot poll. Signed-off-by:
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Chengming Gui authored
Add PSP_V13 memory training support funcs. v2: replace DRM_{DEBUG/ERROR} with dev_{dbg/err}. (Hawking) v3: fix checkpatch error (Alex) Signed-off-by:Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
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Lang Yu authored
No need to reference the BO here, dmabuf framework will handle that. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
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Shikai Guo authored
add get_gfx_off_status interface to yellow_carp_ppt_funcs structure. Signed-off-by:
Shikai Guo <shikai.guo@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Prike Liang <prike.liang@amd.com> Reviewed-by:
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Maíra Canal authored
All references to struct freesync_context were removed, so remove the struct freesync_context itself and its entry on struct dc_stream_state. Reviewed-by:
Maíra Canal <mairacanal@riseup.net> Signed-off-by:
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Chengming Gui authored
Add three additional page fault settings. V2: move reg offset definition to header file. (Alex) V3: add all shift/mask definitions of used reg. (Hawking) Signed-off-by:
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Yang Li authored
Eliminate the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c:2344:67-68: Unneeded semicolon Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Reviewed-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Vijendar Mukunda authored
Fixed following Smatch static checker warning: drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:393 acp_hw_init() error: buffer overflow 'i2s_pdata' 3 <= 3 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:396 acp_hw_init() error: buffer overflow 'i2s_pdata' 3 <= 3 Fixes: 4c33e517 ("drm/amdgpu: create I2S platform devices for Jadeite platform") Reported-by:Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Vijendar Mukunda <Vijendar.Mukunda@amd.com> Acked-by:
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Lang Yu authored
The kgd_mem memory allocated in amdgpu_amdkfd_gpuvm_import_dmabuf() is not freed properly. Explicitly free it in amdgpu_amdkfd_gpuvm_free_memory_of_gpu() under condition "mem->bo->kfd_bo != mem". Suggested-by:
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Alex Sierra authored
This keeps track of kfd system mem used and kfd ttm mem used. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Reviewed-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Alex Sierra authored
[WHY] Unified memory with xnack off should be tracked, as userptr mappings and legacy allocations do. To avoid oversuscribe system memory when xnack off. [How] Exposing functions reserve_mem_limit and unreserve_mem_limit to SVM API and call them on every prange creation and free. Signed-off-by:
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Dan Carpenter authored
The "ret" variable needs to be signed for the error handling to work. Fixes: 2ca97adc ("drm/amd/display: Add Synaptics Fifo Reset Workaround") Signed-off-by:
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Jiapeng Chong authored
No functional modification involved. smatch warnings: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1372 dp_dsc_clock_en_read() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1478 dp_dsc_clock_en_write() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1563 dp_dsc_slice_width_read() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1667 dp_dsc_slice_width_write() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1752 dp_dsc_slice_height_read() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1856 dp_dsc_slice_height_write() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1937 dp_dsc_bits_per_pixel_read() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:2038 dp_dsc_bits_per_pixel_write() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:2117 dp_dsc_pic_width_read() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:2178 dp_dsc_pic_height_read() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:2254 dp_dsc_chunk_size_read() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:2330 dp_dsc_slice_bpg_offset_read() warn: inconsistent indenting. Reported-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Jiapeng Chong authored
Clean up some inconsistent indenting, replace sizeof(x) / sizeof((x)[0])) with ARRAY_SIZE(x). smatch warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.c:185 optc3_fpu_set_vrr_m_const() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.c:355 dcn30_fpu_set_mcif_arb_params() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.c:384 dcn30_fpu_calculate_wm_and_dlg() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.c:390 dcn30_fpu_calculate_wm_and_dlg() warn: inconsistent indenting. Reported-by:
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Jiapeng Chong authored
No functional modification involved. smatch warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.c:205 dcn303_fpu_update_bw_bounding_box() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.c:355 dcn303_fpu_init_soc_bounding_box() warn: inconsistent indenting. Reported-by:
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Jiapeng Chong authored
No functional modification involved. smatch warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:713 dml32_CalculateSwathWidth() warn: inconsistent indenting. Reported-by:
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