- 21 Jan, 2021 10 commits
-
-
Aaron Liu authored
Starting from vangogh, the ATCL2 and DAGB0 registers relative to mgcg/ls has changed. For MGCG: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. For MGLS: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. Add DAGB0_(WR/RD)_CGTT_CLK_CTRL registers. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Jinzhou Su authored
GCR_GENERAL_CNTL is defined differently in gc_10_1_0_offset.h and gc_10_3_0_offset.h. Update GCR_GENERAL_CNTL for Vangogh. Signed-off-by:
Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by:
-
Prike Liang authored
In the renoir there is no need GpuChangeState message set to exit gfxoff in the s0i3 resume since mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL has been added in the s0i3 FSDL. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
-
Vladimir Stempen authored
[why] Heavy corruption or blank screen reported on wake, with 6k display connected and FEC enabled [how] When Disable/Enable stream for display pipes on HPDRX, DC should take into account ODM split pipes. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Vladimir Stempen <vladimir.stempen@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Anson Jacob <anson.jacob@amd.com> Signed-off-by:
-
Nicholas Kazlauskas authored
[Why & How] These can differ per ASIC or not be present. Don't call the dcn20 ones directly but rather the ones defined by the ASIC init table. Tested-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
-
Bing Guo authored
Why: Function decide_dp_link_settings() loops infinitely when required bandwidth can't be supported. How: Check the required bandwidth against verified_link_cap before trying to find a link setting for it. Tested-by:
Bing Guo <bing.guo@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
-
Aric Cyr authored
[Why] When no displays are currently enabled, display driver should not disallow PSTATE switching. [How] Allow PSTATE switching if either the active configuration supports it, or there are no active displays. Tested-by:
-
Jake Wang authored
[WHY] dram clock change latencies get updated using ddr4 latency table, but that update does not happen before validation. This value should not be the default and should be number received from df for better mode support. This may cause a PState hang on high refresh panels with short vblanks such as on 1080p 360hz or 300hz panels. [HOW] Update latency from 23.84 to 11.72. Tested-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
Sung Lee <Sung.Lee@amd.com> Acked-by:
-
Huang Rui authored
The ip discovery is supported on green sardine, it doesn't need gpu info firmware anymore. Signed-off-by:
-
Sung Lee authored
[WHY] Previously as MPO + ODM Combine was not supported, finding secondary pipes for each case was mutually exclusive. Now that both are supported at the same time, both cases should be taken into account when finding a secondary pipe. [HOW] If a secondary pipe cannot be found based on previous bottom pipe, search for a second pipe using next_odm_pipe instead. Tested-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
-
- 15 Jan, 2021 11 commits
-
-
git://github.com/skeggsb/linuxDave Airlie authored
As requested, here's a tree with the non-Ampere-specific fixes split out, as most of them are potentially relevant to already-supported GPUs. - irq handling fix - expansion ROM fix - hw init dpcd disable - aux semaphore owner field fix - vram heap sizing fix - notifier at 0 is valid fix Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Ben Skeggs <skeggsb@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv4P90mcF_ByAh+ghz+ZVD2N2bPbD7xHYYArE1kYrvsGcQ@mail.gmail.com
-
Dave Airlie authored
Merge tag 'amd-drm-fixes-5.11-2021-01-14' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-5.11-2021-01-14: amdgpu: - Update repo location in MAINTAINERS - Add some new renoir PCI IDs - Revert CRC UAPI changes - Revert OLED display fix which cases clocking problems for some systems - Misc vangogh fixes - GFX fix for sienna cichlid - DCN1.0 fix for pipe split - Fix incorrect PSP command amdkfd: - Fix possible out of bounds read in vcrat creation Signed-off-by:
-
Dave Airlie authored
Merge tag 'drm-intel-fixes-2021-01-14' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes drm/i915 fixes for v5.11-rc4: - Allow the sysadmin to override security mitigations - Restore clear-residual mitigations for ivb/byt - Limit VFE threads based on GT - GVT: fix vfio edid and full display detection - Fix DSI DSC power refcounting - Fix LPT CPU mode backlight takeover - Disable RPM wakeref assertions during driver shutdown - Fix DSI sequence sleeps Signed-off-by:
-
Ben Skeggs authored
VRAM offset 0 is a valid address, triggered on GA102. Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
-
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Noticed while debugging GA102. Signed-off-by: -
Ben Skeggs authored
RM does this around transactions, and it seemed to help while debugging AUXCH issues on GA102. Signed-off-by: -
Ben Skeggs authored
No functional changes here yet. Signed-off-by: -
Ben Skeggs authored
Whatever it is that we were doing before doesn't work on Ampere. Signed-off-by: -
Ben Skeggs authored
This issue has generally been covered up by the presence of additional expansion ROMs after the ones we're interested in, with header fetches of subsequent images loading enough of the ROM to hide the issue. Noticed on GA102, which lacks a type 0x70 image compared to TU102,. [ 906.364197] nouveau 0000:09:00.0: bios: 00000000: type 00, 65024 bytes [ 906.381205] nouveau 0000:09:00.0: bios: 0000fe00: type 03, 91648 bytes [ 906.405213] nouveau 0000:09:00.0: bios: 00026400: type e0, 22016 bytes [ 906.410984] nouveau 0000:09:00.0: bios: 0002ba00: type e0, 366080 bytes vs [ 22.961901] nouveau 0000:09:00.0: bios: 00000000: type 00, 60416 bytes [ 22.984174] nouveau 0000:09:00.0: bios: 0000ec00: type 03, 71168 bytes [ 23.010446] nouveau 0000:09:00.0: bios: 00020200: type e0, 48128 bytes [ 23.028220] nouveau 0000:09:00.0: bios: 0002be00: type e0, 140800 bytes [ 23.080196] nouveau 0000:09:00.0: bios: 0004e400: type 70, 7168 bytes Signed-off-by: -
git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
Short summary of fixes pull: * dma-buf: Fix a memory leak in CMAV heap * drm: Fix format check for legacy pageflips * ttm: Pass correct address to dma_mapping_error(); Use mutex in pool shrinker Signed-off-by:
-
- 14 Jan, 2021 18 commits
-
-
Wayne Lin authored
[Why] Find out when we try to disable CRC calculation, crc generation is still enabled. Main reason is that dc_stream_configure_crc() will never get called when the source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE. [How] Add checking condition that when source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE, we should also call dc_stream_configure_crc() to disable crc calculation. Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Signed-off-by:
-
Rodrigo Siqueira authored
This reverts commit c920888c. Cc: Wayne Lin <Wayne.Lin@amd.com> Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Roman Li <Roman.Li@amd.com> Cc: Bindu R <Bindu.R@amd.com> Cc: Daniel Vetter <daniel@ffwll.ch> Acked-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by:
-
Rodrigo Siqueira authored
This reverts commit 6ae09fa4. Cc: Wayne Lin <Wayne.Lin@amd.com> Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Roman Li <Roman.Li@amd.com> Cc: Bindu R <Bindu.R@amd.com> Cc: Daniel Vetter <daniel@ffwll.ch> Acked-by:
-
Rodrigo Siqueira authored
This reverts commit f01afd1e. Cc: Wayne Lin <Wayne.Lin@amd.com> Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Roman Li <Roman.Li@amd.com> Cc: Bindu R <Bindu.R@amd.com> Cc: Daniel Vetter <daniel@ffwll.ch> Acked-by:
-
Likun Gao authored
Add function to set power brake sequence. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
-
mengwang authored
add DID 0x164C into pciidlist under CHIP_RENOIR family. Signed-off-by:
mengwang <mengbing.wang@amd.com> Reviewed-by:
-
Prike Liang authored
Add green_sardine PCI id support and map it to renoir asic type. v2: add apu flag Signed-off-by:
-
Huang Rui authored
This patch is to update atomfirmware parser for the memory type and bandwidth of DDR5 and DDR4. Signed-off-by:
-
chen gong authored
The address of the GOLDEN_TSC_COUNT_UPPER/GOLDEN_TSC_COUNT_LOWER for Vnagogh are different from the others. The offset of the GOLDEN_TSC_COUNT_UPPER for Vangogh is 0x0025 by calculation. The offset of the GOLDEN_TSC_COUNT_LOWER for Vangogh is 0x0026 by calculation. Signed-off-by:
chen gong <curry.gong@amd.com> Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
-
Jeremy Cline authored
KASAN reported a slab-out-of-bounds read of size 1 in kdf_create_vcrat_image_cpu(). This occurs when, for example, when on an x86_64 with a single NUMA node because kfd_fill_iolink_info_for_cpu() is a no-op, but afterwards the sub_type_hdr->length, which is out-of-bounds, is read and multiplied by entries. Fortunately, entries is 0 in this case so the overall crat_table->length is still correct. Check if there were any entries before de-referencing sub_type_hdr which may be pointing to out-of-bounds memory. Fixes: b7b6c385 ("drm/amdkfd: Calculate CPU VCRAT size dynamically (v2)") Suggested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Jeremy Cline <jcline@redhat.com> Reviewed-by:
-
Rodrigo Siqueira authored
commit a861736d ("drm/amd/display: Fixed Intermittent blue screen on OLED panel") causes power regression for many users. It seems that this change causes the MCLK to get forced high; this creates a regression for many users since their devices were not able to drop to a low state after this change. For this reason, this reverts commit a861736d. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1407 Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Naveed Ashfaq <Naveed.Ashfaq@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Roman Li <roman.li@amd.com> Acked-by:
-
Li, Roman authored
[Why] The initial purpose of dcn10 pipe split is to support some high bandwidth mode which requires dispclk greater than max dispclk. By initial bring up power measurement data, it showed power consumption is less with pipe split for dcn block. This could be reason for enable pipe split by default. By battery life measurement of some Chromebooks, result shows battery life is longer with pipe split disabled. [How] Disable pipe split by default. Pipe split could be still enabled when required dispclk is greater than max dispclk. Tested-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
-
Nikola Cornij authored
[why] Required for DSC MST Tested-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Zhan Liu <Zhan.Liu@amd.com> Acked-by:
-
Wesley Chalmers authored
[WHY] The stack variable "val" is potentially unpopulate it, so initialize it with the value 0xf (indicating an invalid mux) Tested-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
-
Qingqing Zhuo authored
[Why] In dc_link_dp_set_test_pattern, we assume all pipes have a stream, which can cause null pointer dereference. [How] Add a null pointer check before accessing stream. Tested-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
-
Victor Zhao authored
psp GFX_CTRL_CMD_ID_CONSUME_CMD different for windows and linux, according to psp, linux cmds are not correct. v2: only correct GFX_CTRL_CMD_ID_CONSUME_CMD. Signed-off-by:
Victor Zhao <Victor.Zhao@amd.com> Reviewed-by:
Emily.Deng <Emily.Deng@amd.com> Signed-off-by:
-
Alexandre Demers authored
This fix bug 210921 where DRM_INFO floods log when hitting an unsupported ASIC in amdgpu_device_asic_has_dc_support(). This info should be only called once. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=210921Signed-off-by:
Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by:
-
Alex Deucher authored
FDO is out of space, so move to gitlab. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
-
- 12 Jan, 2021 1 commit
-
-
Chris Wilson authored
The clear-residuals mitigation is a relatively heavy hammer and under some circumstances the user may wish to forgo the context isolation in order to meet some performance requirement. Introduce a generic module parameter to allow selectively enabling/disabling different mitigations. To disable just the clear-residuals mitigation (on Ivybridge, Baytrail, or Haswell) use the module parameter: i915.mitigations=auto,!residuals Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1858 Fixes: 47f8253d ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jon Bloomfield <jon.bloomfield@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: stable@vger.kernel.org # v5.7 Reviewed-by:
Jon Bloomfield <jon.bloomfield@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111225220.3483-3-chris@chris-wilson.co.uk (cherry picked from commit f7452c7c) Signed-off-by:
Jani Nikula <jani.nikula@intel.com>
-
