- 25 Jul, 2022 40 commits
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Melissa Wen authored
Move remaining FPU code to DML folder that caused compilation error for powerpc. This patch depends on [1] to prevent the error below: /gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_resource.o uses soft float /gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: failed to merge target specific data of file drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_resource.o /gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/amdgpu/../display/dc/dcn315/dcn315_resource.o uses soft float /gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: failed to merge target specific data of file drivers/gpu/drm/amd/amdgpu/../display/dc/dcn315/dcn315_resource.o /gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/amdgpu/../display/dc/dcn316/dcn316_resource.o uses soft float /gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: failed to merge target specific data of file drivers/gpu/drm/amd/amdgpu/../display/dc/dcn316/dcn316_resource.o [1] https://lore.kernel.org/amd-gfx/20220716195144.342960-1-mwen@igalia.com/Reported-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
Melissa Wen <mwen@igalia.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Aric Cyr authored
This version brings along following fixes: - Isolate FPU operation for DCN32/321 under the DML folder - Create a specific file for CRTC and plane based on amdgpu_dm - Fix DSC issues - Update DML logic Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
This commit fully move the missing FPU operations from dcn321 resource to dcn321 fpu. It also remove those FPU flags from the Makefile. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
The file dcn321_resource has a lot of FPU operations that should be inside the dml folder. This commit introduces the dcn321_fpu file and moves some of the FPU operation functions to this new file. Tested-by:
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Rodrigo Siqueira authored
This is the final commit from the FPU isolation for DCN32 and for this reason we can finally remove flags related to FPU. Tested-by:
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Rodrigo Siqueira authored
The final part of the DCN32 code that uses FPU is the bounding box code, and this commit move it to dcn32_fpu. Tested-by:
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Rodrigo Siqueira authored
Move get_optimal_ntuple to the FPU code and call it inside insert_entry_into_table_sorted. Tested-by:
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Rodrigo Siqueira authored
Move dlg params calculation to the FPU folder and make it static. Tested-by:
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Rodrigo Siqueira authored
Move dcn32_calculate_wm_and_dlg from dcn32 resources to the FPU code. Additionally, this commit adds an interface to it. Tested-by:
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Rodrigo Siqueira authored
It looks like many of the code related to SubVP uses FPU operation, and we have many static functions that are part of this feature. This commit is a little bit large, but it only moves SubVP operation from one file to another, and I had to do it in a single change due to dependencies between functions. Tested-by:
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Rodrigo Siqueira authored
This commit moves phanton FPU stream to dcn32_fpu file. Tested-by:
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Rodrigo Siqueira authored
The insert_entry_into_table_sorted function uses FPU operation and calls other static functions support. This commit moves the insert entry function with all the required struct and static functions to the FPU file. Tested-by:
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Rajneesh Bhardwaj authored
This simplifies existing coherence handling for Arcturus and Aldabaran to account for !coherent && uncached scenarios. Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
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Chengming Gui authored
Support {GLOBAL/SE0/SE1/SE2/SE3}_TAP_DELAYS uploading. v2: upload TAP_DELAYS before RLC autoload was triggered. (Hawking) Signed-off-by:Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Evan Quan authored
The current approach breaks S3/S4 as asic reset is needed for them. And putting SMU out of service(via SMU_MSG_PrepareMp1ForUnload) will make that(asic reset) failed. Considering with current designs, there is actually also asic reset involved on driver reloading. That can make asic back to a clean state. So, the SMU_MSG_PrepareMp1ForUnload operation will be not so necessary. Thus we will just drop the SMU_MSG_PrepareMp1ForUnload operation. We may revise the whole driver reloading sequences when there is a better design. Fixes: 72aeb6ee ("drm/amd/pm: fix driver reload SMC firmware fail issue for smu13") Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
Only PP_MP1_STATE_UNLOAD is supported for now. For other mp1 state, we should just ignore it. Otherwise, there will be errors coming out. Signed-off-by:
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Evan Quan authored
To fit the latest 78.49.0 PMFW. Also, bump the version to 0x2B. Signed-off-by:
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Evan Quan authored
The feature is ready with latest firmwares. Signed-off-by:
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Kenneth Feng authored
update driver if header for smu_13_0_7 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Acked-by:
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Rodrigo Siqueira authored
The function dcn32_predict_pipe_split uses FPU operations. This commit moves this function to the dcn32_fpu file, and we ensure that we only invoke it under the kernel_fpu protection. Tested-by:
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YiPeng Chai authored
Add ras eeprom i2c function for smu13 v13_0_0. Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Acked-by:
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Leo Li authored
[Why & How] It's useful to disable MPO when debugging or testing. Therefore, add a dcdebugmask option to disable MPO. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
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Leo Li authored
[Why] Being able to configure visual confirm at boot or in cmdline is helpful when debugging. [How] Add a module parameter to configure DC visual confirm, which works the same way as the equivalent debugfs entry. Signed-off-by:
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Rodrigo Siqueira authored
The function dcn32_helper_populate_phantom_dlg_params uses FPU operations. For this reason, this commit moves this function to the dcn32_fpu file, and we ensure that we only invoke it under the kernel_fpu protection. Tested-by:
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Alex Deucher authored
So userspace knows when it is available. Proposed mesa patch: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411/diffs?commit_id=c8a63590dfd0d64e6e6a634dcfed993f135dd075Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Alex Deucher authored
Use the former pad element to store the IP versions from the IP discovery table. This allows userspace to get the IP version from the kernel to better align with hardware IP versions. Proposed mesa patch: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411/diffs?commit_id=c8a63590dfd0d64e6e6a634dcfed993f135dd075Reviewed-by:
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Rodrigo Siqueira authored
We are working to isolate FPU operations inside the DML folder, and the file dcn32_clk_mgr has some of these operations. This commit moves the FPU operations inside the clock manager and creates the dcn32_fpu file to aggregate those operations. Note that there is no functional change ere, just moving code from one part to another. Tested-by:
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Aurabindo Pillai authored
This reverts commit e7ef5569e71bf3fec01ea513c27c6081c0dbbc64. Idle optimization was disabled due to SMU and firmware bugs. Enable it back for DCN32. DCN321 has them enabled already Fixes: 6a640b95 ("drm/amd/display: disable idle optimizations") Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-and-tested-by:
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Jun Lei authored
[why] Unbounded request logic in resource/DML has some issues where unbounded request is being enabled incorrectly. SW today enables unbounded request unconditionally in hardware, on the assumption that HW can always support it in single pipe scenarios. This worked until now because the same assumption is made in DML. A new DML update is needed to fix a bug, where there are single pipe scenarios where unbounded cannot be enabled, and this change in DML needs to be ported in, and dcn32 resource logic fixed. [how] First, dcn32_resource should program unbounded req in HW according to unbounded req enablement output from DML, as opposed to DML input. Second, port in DML update which disables unbounded req in some scenarios to fix an issue with poor stutter performance Tested-by:
Jun Lei <jun.lei@amd.com> Signed-off-by:
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Chris Park authored
[Why] Cursor size can update without MALL cache update. Update the register on cursor attribute as well. [How] Update cursor MALL cache on cursor attribute update. Tested-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
Chris Park <chris.park@amd.com> Signed-off-by:
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Jason Wang authored
The double `to' is duplicated in the comment, remove one. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Jason Wang <wangborong@cdjrlc.com> Signed-off-by:
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Jason Wang authored
The double `have' is duplicated in line 696, remove one. Reviewed-by:
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Roman Li authored
Adding dm ip block to enable display on dcn 3.1.4. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Roman Li authored
[Why] DCN 3.1.4 uses dmub not dmcu. Attempt to identify dmcu firmware for dcn314 results in dm init error: "Unsupported ASIC type" [How] Add dcn314 to the list of asics that don't require dmcu Signed-off-by:
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Taimur Hassan authored
[Why & How] There are cases where the pipes populated are not all at the top of the pipes list under context. Loop through all pipes for DET allocation instead of just the number of populated ones, even if some unpopulated pipes are iterated through unnecessarily. Tested-by:
Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by:
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Vladimir Stempen authored
[Why] VM enabled in IP configuration causes UCLK not reaching DPM0. The expectation for VM enable should be that KMD will indicate to DAL when VM is enabled, then DAL will set the bit accordingly [How] Set gpuvm_enable to zero in DCN3_20 and DCN3_21 resource. Tested-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Vladimir Stempen <vladimir.stempen@amd.com> Signed-off-by:
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André Almeida authored
Add a GFXOFF section at "GPU Power Controls" file, explaining what it is and how userspace can interact with it. v2: minor tweaks to the documenation (Alex) Signed-off-by:
André Almeida <andrealmeid@igalia.com> Signed-off-by:
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André Almeida authored
GFXOFF has two different "state" values: one to define if the GPU is allowed/disallowed to enter GFXOFF, usually called state; and another one to define if currently GFXOFF is being used, usually called status. Even when GFXOFF is allowed, GPU firmware can decide to not used it accordingly to the GPU load. Userspace can allow/disallow GPUs to enter into GFXOFF via debugfs. The kernel maintains a counter of requests for GFXOFF (gfx_off_req_count) that should be decreased to allow GFXOFF and increased to disallow. The issue with this interface is that userspace can't be sure if GFXOFF is currently allowed. Even by checking amdgpu_gfxoff file, one might get an ambiguous 2, that means that GPU is currently out of GFXOFF, but that can be either because it's currently disallowed or because it's allowed but given the current GPU load it's enabled. Then, userspace needs to rely on the fact that GFXOFF is enabled by default on boot and to track this information. To make userspace life easier and GFXOFF more reliable, return the current state of GFXOFF to userspace when reading amdgpu_gfxoff with the same semantics of writing: 0 means not allowed, not 0 means allowed. Expose the current status of GFXOFF through a new file, amdgpu_gfxoff_status. Signed-off-by:
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Melissa Wen authored
Although dcn31_update_soc_for_wm_a() is only called in dml/dcn31/dcn31_fpu by dc->res_pool->funcs->update_soc_for_wm_a(dc, context), it's declared in dcn31_resource that is not FPU protected. Move this function to dcn31_fpu file as part of the work to isolate FPU code. Signed-off-by:
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Maíra Canal authored
Remove the variable MaxUsedBW from the function DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation. As a side-effect, the variables MaxPerPlaneVActiveWRBandwidth and WRBandwidth are also removed. This was pointed by clang with the following warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:3043:10: warning: variable 'MaxUsedBW' set but not used [-Wunused-but-set-variable] double MaxUsedBW = 0; ^ 1 warning generated. Reviewed-by:Maíra Canal <mairacanal@riseup.net> Signed-off-by:
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