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- 06 Aug, 2020 1 commit
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Evan Quan authored
Thus we can provide an interface for UMD to retrieve gpu metrics data. V2: better naming and comments V3: two structures created for dGPU and APU separately V4: add driver attached timestamp Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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- 06 Nov, 2019 1 commit
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Evan Quan authored
Add xgmi pstate setting on powerplay routine. V2: split the change of is_support_sw_smu_xgmi into a separate patch Signed-off-by:
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- 15 Oct, 2019 1 commit
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Evan Quan authored
Currently this is only supported on Vega20 with 40.50 and later SMC firmware. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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- 27 Aug, 2019 1 commit
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Andrey Grodzovsky authored
v2: PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict over I2C bus and engine disable thermal control access to force SMU stop using the I2C bus until the issue is reslolved. Expose and call vega20_is_smc_ram_running to skip locking when SMU FW is not yet loaded. v3: Remove the prevoius hack as the SMU found the bug. v5: Typo fix Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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- 15 Aug, 2019 1 commit
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Andrey Grodzovsky authored
Add callback to call the new mode2 reset interface. Signed-off-by:
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- 31 Jul, 2019 3 commits
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Evan Quan authored
VCN is widely used in new ASICs and different from tranditional UVD and VCE. Signed-off-by:
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Evan Quan authored
VCN is widely used in new ASICs and different from tranditional UVD and VCE. Signed-off-by:
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Alex Deucher authored
This is required for certain cases such as various GPU resets (mode1, mode2), BACO, shutdown, unload, etc. to put the SMU into the appropriate state for when the hw is re-initialized. Reviewed-by:
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- 18 Jul, 2019 1 commit
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Evan Quan authored
Current implementation is not actually able to detect invalid message/table/workload mapping. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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- 24 May, 2019 3 commits
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Evan Quan authored
Enable realtime memory utilization report on Vega20. Signed-off-by:
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Evan Quan authored
Expose temp[1-3]_label hwmon interfaces. While temp2_label and temp3_label are visible for SOC15 dGPUs only. - V2: correct temp1_label as "edge" Signed-off-by:
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Evan Quan authored
Two new hwmon interfaces(temp2_input and temp3_input) are added. They are supported on SOC15 dGPUs only. - V2: correct thermal sensor output Signed-off-by:
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- 25 Jan, 2019 4 commits
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Evan Quan authored
User can use "pp_dpm_dcefclk" to retrieve and adjust dcefclock power levels. V2: expose this interface for Vega10 and later ASICs only Signed-off-by:
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Evan Quan authored
User can use "pp_dpm_fclk" to retrieve and adjust fclock power levels. V2: expose this interface for Vega20 and later ASICs only Signed-off-by:
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Evan Quan authored
User can use "pp_dpm_socclk" to retrieve and adjust SOC clock power levels. V2: expose this interface for Vega10 and later ASICs only Signed-off-by:
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Evan Quan authored
User can use "ppfeatures" sysfs interface to retrieve and set enabled powerplay features. V2: expose this feature for Vega10 and later dGPUs V3: squash in removal of unused variable (Alex) Signed-off-by:
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- 14 Jan, 2019 2 commits
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Jim Qu authored
Signed-off-by:
Jim Qu <Jim.Qu@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Evan Quan authored
This can avoid unexpected profile mode change after running compute workload. Signed-off-by:
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- 02 Jan, 2019 1 commit
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Evan Quan authored
This can avoid unexpected profile mode change after running compute workload. Signed-off-by:
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- 07 Dec, 2018 1 commit
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hersen wu authored
[WHY] clarify dal input parameters to pplib interface, remove un-used parameters. dal knows exactly which parameters needed and their effects at pplib and smu sides. current dal sequence for dcn1_update_clock to pplib: 1.smu10_display_clock_voltage_request for dcefclk 2.smu10_display_clock_voltage_request for fclk 3.phm_store_dal_configuration_data { set_min_deep_sleep_dcfclk set_active_display_count store_cc6_data --- this data never be referenced new sequence will be: 1. set_display_count --- need add new pplib interface 2. set_min_deep_sleep_dcfclk -- new pplib interface 3. set_hard_min_dcfclk_by_freq 4. set_hard_min_fclk_by_freq after this code refactor, smu10_display_clock_voltage_request, phm_store_dal_configuration_data will not be needed for rv. [HOW] step 1: add new functions at pplib interface step 2: add new functions at amdgpu dm and dc Signed-off-by:hersen wu <hersenxs.wu@amd.com> Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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- 09 Oct, 2018 3 commits
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Rex Zhu authored
Add fan1_target for get/set fan speed in RPM unit Add fan1_min/fan1_max for get min, max fan speed in RPM unit Add fan1_enable to enable/disable the fan1 sensor v3: drop the hardcode value of min/max rpm in comments pointed out by Alex. v2: query the min/max rpm gpu support instand of hardcode value. Reviewed-by: -
Rex Zhu authored
For getting the min/max fan speed in RPM units. Reviewed-by:
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Evan Quan authored
MGPU fan boost feature is enabled only when two or more dGPUs in the system. Signed-off-by:
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- 27 Sep, 2018 1 commit
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Alex Deucher authored
For getting the 64 bit enabled smc feature mask from vega parts. Reviewed-by:
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- 11 Sep, 2018 1 commit
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Evan Quan authored
Added vega20 overdrive support based on existing OD sysfs APIs. However, the OD logics are simplified on vega20. So, the behavior will be a little different and works only on some limited levels. V2: fix typo fix commit description revise error logs add support for clock OD V3: separate clock from voltage OD settings Signed-off-by:
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- 05 Jul, 2018 4 commits
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Rex Zhu authored
Display can notify smu to enable pwe after gpu suspend. It is used in case when display resumes from S3 and wants to start audio driver by enabling pwe Acked-by:
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Rex Zhu authored
use void * as function parameter type in order for extension. Acked-by:
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Rex Zhu authored
Some HW ip blocks need call SMU to enter/leave power gate state. So export common set_powergating_by_smu interface. 1. keep consistent with set_clockgating_by_smu 2. scales easily to powergate other ip(gfx) if necessary Reviewed-by:
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Rex Zhu authored
In order to keep consistent with powergate_uvd/vce. Reviewed-by:
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- 15 May, 2018 3 commits
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Rex Zhu authored
when user cat pp_od_clk_voltage add display info about the sclk/mclk/vddc range that user can overdrive output as: OD_SCLK: 0: 300MHz 900mV 1: 400MHz 912mV 2: 500MHz 925mV 3: 600MHz 937mV 4: 700MHz 950mV 5: 800MHz 975mV 6: 900MHz 987mV 7: 1000MHz 1000mV OD_MCLK: 0: 300MHz 900mV 1: 1500MHz 912mV OD_RANGE: SCLK: 300MHz 1200MHz MCLK: 300MHz 1500MHz VDDC: 700mV 1200mV also 1. remove unnecessary whitespace before a quoted newline 2. change unit of frequency Mhz to MHz Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
Currently smu only calculate average gpu power in real time. for vddc/vddci/max power, User need to set start time and end time, firmware can calculate the average vddc/vddci/max power. but the type of return values is not unified. For Vi, return type is uint. For vega, return type is float. so this struct can't be suitable for all asics. Acked-by:
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- 15 Mar, 2018 1 commit
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Rex Zhu authored
1. delete amdgpu_powerplay.c used for wrapping smu ip functions 2. delete struct pp_instance, 3. make struct hwmgr as the smu hw handle. Reviewed-by:
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- 07 Mar, 2018 1 commit
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Rex Zhu authored
Add power profiling mode dynamic switch based on the workloads. Currently, support Cumpute, VR, Video, 3D,power saving with Cumpute have highest prority, power saving have lowest prority. in manual dpm mode, driver will stop auto switch, just save the client's requests. user can set power profiling mode through sysfs. when exit manual dpm mode, driver will response the client's requests. switch based on the client's prority. v2: squash in fixes from Rex Reviewed-by:
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- 06 Mar, 2018 1 commit
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Rex Zhu authored
The gfx/compute profiling mode switch is only for internally test. Not a complete solution and unexpectly upstream. so revert it. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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- 05 Mar, 2018 1 commit
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Rex Zhu authored
use adev as input parameter to create powerplay instance directly. delete cgs wrap layer for power play create. Reviewed-by:
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- 19 Feb, 2018 4 commits
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Rex Zhu authored
User can change power limit between [0, 1] * max power limit. Set power limit to 0, restore to max power limit. Reviewed-by:
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Eric Huang authored
Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Alex Deucher authored
This is also supported with the read_sensor API and there were no more users of the get_temperature API. Acked-by:
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Rex Zhu authored
when cat pp_od_clk_voltage it show OD_SCLK: 0: 300Mhz 800 mV 1: 466Mhz 818 mV 2: 751Mhz 824 mV 3: 1019Mhz 987 mV 4: 1074Mhz 1037 mV 5: 1126Mhz 1087 mV 6: 1169Mhz 1137 mV 7: 1206Mhz 1150 mV OD_MCLK: 0: 300Mhz 800 mV 1: 1650Mhz 1000 mV echo "s/m level clock voltage" to change sclk/mclk's clock and voltage echo "r" to restore default value. echo "c" to commit the user setting. Reviewed-by:
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