- 29 Mar, 2021 12 commits
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Dong Aisheng authored
The CONN SS of MX8QM is mostly the same as MX8QXP except it has one more USB HSIC module support. So we can fully reuse the exist CONN SS dtsi. Add <soc>-ss-conn.dtsi with compatible string updated according to imx8-ss-conn.dtsi. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Dong Aisheng authored
The LSIO SS of MX8QM is exactly the same as MX8QXP. So we can fully reuse the exist LSIO SS dtsi. Add <soc>-ss-lsio.dtsi with compatible string updated according to imx8-ss-lsio.dtsi. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Dong Aisheng authored
switch to new lpcg clock binding Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Dong Aisheng authored
switch to two cell scu clock binding Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Dong Aisheng authored
Add adma lpcg clocks Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Dong Aisheng authored
Add conn lpcg clocks Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Dong Aisheng authored
Add lsio lpcg clocks Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Dong Aisheng authored
MX8 SoC is comprised of a few HW subsystems while some of them can be reused in the different SoCs. So let's re-orginize them into subsystems in device tree as well for the possible reuse of the common part. Note, as there's still no devices of hsio subsys, so removed it first instead of creating a subsys headfile with no devices. They will be added back when new devices added. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Dong Aisheng authored
SCU clock depends on SCU Power domain. Moving scu pd node before scu clock can save a hundred of defer probes of all system devices which depends on power domain and clocks. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Dong Aisheng authored
According to binding doc, add the fallback compatible string for scu pd. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Peng Fan authored
There is wdog[2,3] in i.MX8MP, so add them. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Heiko Thiery authored
The Kontron pitx-imx8m board is based on an i.MX8MQ soc. Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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- 15 Mar, 2021 26 commits
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Marek Vasut authored
The board has both MACs routed out, enable the EQOS. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Heiko Schocher <hs@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Marek Vasut authored
Add EQOS GMAC node per Documentation/devicetree/bindings/net/imx-dwmac.txt , leave out the nvmem entries as that is not yet available, so the MAC has to be passed in via DT by the bootloader. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Heiko Schocher <hs@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Jagan Teki authored
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. i.Core MX8M Mini needs to mount on top of this Evaluation board for creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit. PCIe, DSI, CSI nodes will add it into imx8mm-engicam-edimm2.2.dtsi once Mainline Linux supported. Add support for it. Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Jagan Teki authored
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. i.Core MX8M Mini needs to mount on top of this Carrier board for creating complete i.Core MX8M Mini C.TOUCH 2.0 board. Add support for it. Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Jagan Teki authored
i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. General features: - NXP i.MX8M Mini - Up to 2GB LDDR4 - 8/16GB eMMC - Gigabit Ethernet - USB 2.0 Host/OTG - PCIe Gen2 interface - I2S - MIPI DSI to LVDS - rest of i.MX8M Mini features i.Core MX8M Mini needs to mount on top of Engicam baseboards for creating complete platform solutions. Add support for it. Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Peng Fan authored
Per dt-bindings, the clock-names sequence should be ipg ahb per to pass dtbs_check. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Adrien Grassein authored
Add audio description and pin muxing. Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Adrien Grassein authored
Add FlexSPI description an pin muxing. Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Adrien Grassein authored
Add description for the four PWMs. Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Adrien Grassein authored
Remove useless clocks in UART 2 Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Adrien Grassein authored
Add description and pin muxing for UARTs. Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Adrien Grassein authored
Add description of USB. usbotg2 seems to not working on all boards (including ones from variscite). Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Adrien Grassein authored
Add VMMC and VQMMC description for USDHC1 (eMMC). There are comming directly from the alimentation stage, so add the vref_3V3 fixed regulator. Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Adrien Grassein authored
Add usdhc3 description which corresponds to the wifi/bt chip Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Guido Günther authored
This allows for automatic output source switching in userspace. Enable the pullup on the GPIO to actually make it trigger and mark it as active-high since detection is reversed otherwise. Signed-off-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Guido Günther authored
Add mux so we can select either headset or built-in microphone input. Signed-off-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Guido Günther authored
The SGTL500s LINEINL and LINEINR are N/C. Signed-off-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Guido Günther authored
Wire up the amplifier that drives the builtin speaker. Signed-off-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Guido Günther authored
The codec is currently named after the chip but it should be named like the device itself since otherwise it's impossible to distinguish it from other devices using the same codec (e.g. in alsa's UCM). Signed-off-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Martin Kepplinger authored
On Birch I can never reach 220 and hence the display would never turn off. Tests suggest 120 to be a good threshold value for all Birch devices. Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Angus Ainslie authored
These sections should be read only as they contain important data. Signed-off-by: Angus Ainslie <angus@akkea.ca> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Guido Günther authored
IMX8MQ_AUDIO_PLL1 and IMX8MQ_AUDIO_PLL2 are setup to the same rates right on the clock controller. Signed-off-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Guido Günther authored
The PMIC driver now sets appropriate default delays. Signed-off-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Adam Ford authored
Enable 100Mhz and 200MHz pinmux and corrsesponding voltage supplies to enable SDR104 on usdhc1 connecting the WiFi chip. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Michael Walle authored
The legacy interrupt INT_A is hardwired to the event collector. RCEC is bascially supported starting with v5.11. Having a correct interrupt, will make RCEC at least probe correctly. There are still issues with how RCEC is implemented in the RCiEP on the LS1028A. RCEC will report an error, but it cannot find the correct subdevice. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Fabio Estevam authored
Pass the i2c3 unit name to fix the following W=1 build warning: arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts:159.8-172.5: Warning (unit_address_vs_reg): /soc@0/bus@30800000/i2c@30a40000/i2cmux@70/i2c3: node has a reg or ranges property, but no unit name Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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- 06 Mar, 2021 2 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdmaLinus Torvalds authored
Pull rdma fixes from Jason Gunthorpe: "Nothing special here, though Bob's regression fixes for rxe would have made it before the rc cycle had there not been such strong winter weather! - Fix corner cases in the rxe reference counting cleanup that are causing regressions in blktests for SRP - Two kdoc fixes so W=1 is clean - Missing error return in error unwind for mlx5 - Wrong lock type nesting in IB CM" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: RDMA/rxe: Fix errant WARN_ONCE in rxe_completer() RDMA/rxe: Fix extra deref in rxe_rcv_mcast_pkt() RDMA/rxe: Fix missed IB reference counting in loopback RDMA/uverbs: Fix kernel-doc warning of _uverbs_alloc RDMA/mlx5: Set correct kernel-doc identifier IB/mlx5: Add missing error code RDMA/rxe: Fix missing kconfig dependency on CRYPTO RDMA/cm: Fix IRQ restore in ib_send_cm_sidr_rep
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