- 14 Feb, 2023 8 commits
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Alvin Lee authored
[Why & How] - For prefetch max vratio check, use the calculated prefetch bandwidth from dml32_CalculatePrefetchSchedule instead of max prefetch bandwidth - Also multiply prefetch bandwidth by VRatio since scaling is not considered one calculating require prefetch bw Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicholas Kazlauskas authored
[Why] To align with DCN31 behavior. This helps avoid p-state hangs in the case where underflow does occur. [How] Flip the bit to true. Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why & How] When k1 and k2 divider programming logic is executed for a phantom stream, the corresponding master stream should be used for the calculation. Fix the if condition to use the master stream for checking signal type instead of the phantom stream. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Single 4K60 playing YUV420 MPO video blocks P-State because the required VRatio for prefetch is too high (luma plane for YUV420 is 1bpe, so swath height is 16 and prefetch requires more lines) - Allow max vratio per plane to be 7.9 for single display YUV420 MPO video cases - Ensure that global vratio prefetch (i.e. total prefetch BW vs. total active bandwidth) does not excited 4.0 Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] DOMAIN power gating control is now required to be done via firmware due to interlock with other power features. This is to avoid intermittent issues in the LB memories. [How] If the firmware supports the command then use the new firmware as the sequence can avoid potential display corruption issues. The command will be ignored on firmware that does not support DOMAIN power control and the pipes will remain always on - frequent PG cycling can cause the issue to occur on the old sequence, so we should avoid it. Reviewed-by:
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Kenneth Feng authored
implement mode2 reset on smu_v13_0_10 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Xiaogang Chen authored
When xnack is on user space can use svm page restore to set a vm range without setup it first, then use regular api to register. Currently kfd api and svm are not interoperable. We already have check on that, but for user buffer the mapping address is not same as buffer cpu virtual address. Add checking on that to avoid error propagate to hmm. Signed-off-by:
Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Ma Jun authored
Checking INVOKE_CMD to fix the below warning info when unload or remove amdgpu driver [ 319.489809] Call Trace: [ 319.489810] <TASK> [ 319.489812] psp_ta_unload+0x9a/0xd0 [amdgpu] [ 319.489926] ? smu_smc_hw_cleanup+0x2f6/0x360 [amdgpu] [ 319.490072] psp_hw_fini+0xea/0x170 [amdgpu] [ 319.490231] amdgpu_device_fini_hw+0x2fc/0x413 [amdgpu] [ 319.490398] ? blocking_notifier_chain_unregister+0x56/0xb0 [ 319.490401] amdgpu_driver_unload_kms+0x51/0x60 [amdgpu] [ 319.490493] amdgpu_pci_remove+0x5a/0x140 [amdgpu] [ 319.490583] ? __pm_runtime_resume+0x60/0x90 [ 319.490586] pci_device_remove+0x3b/0xb0 [ 319.490588] __device_release_driver+0x1a8/0x2a0 [ 319.490591] driver_detach+0xf3/0x140 [ 319.490593] bus_remove_driver+0x6c/0xf0 [ 319.490595] driver_unregister+0x31/0x60 [ 319.490597] pci_unregister_driver+0x40/0x90 [ 319.490599] amdgpu_exit+0x15/0x44e [amdgpu] Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
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- 09 Feb, 2023 15 commits
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Alex Deucher authored
This reverts commit 3cc67fe1. Some users have reported flickerng with S/G display. We've tried extensively to reproduce and debug the issue on a wide variety of platform configurations (DRAM bandwidth, etc.) and a variety of monitors, but so far have not been able to. We disabled S/G display on a number of platforms to address this but that leads to failure to pin framebuffers errors and blank displays when there is memory pressure or no displays at all on systems with limited carveout (e.g., Chromebooks). We have a parameter to disable this as a debugging option as a way for users to disable this, depending on their use case, and for us to help debug this further. Having this enabled seems like the lesser of to evils. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
This reverts commit 2404f9b0. Some users have reported flickerng with S/G display. We've tried extensively to reproduce and debug the issue on a wide variety of platform configurations (DRAM bandwidth, etc.) and a variety of monitors, but so far have not been able to. We disabled S/G display on a number of platforms to address this but that leads to failure to pin framebuffers errors and blank displays when there is memory pressure or no displays at all on systems with limited carveout (e.g., Chromebooks). We have a parameter to disable this as a debugging option as a way for users to disable this, depending on their use case, and for us to help debug this further. Having this enabled seems like the lesser of to evils. Reviewed-by:
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Alex Deucher authored
This reverts commit f081cd4c. Some users have reported flickerng with S/G display. We've tried extensively to reproduce and debug the issue on a wide variety of platform configurations (DRAM bandwidth, etc.) and a variety of monitors, but so far have not been able to. We disabled S/G display on a number of platforms to address this but that leads to failure to pin framebuffers errors and blank displays when there is memory pressure or no displays at all on systems with limited carveout (e.g., Chromebooks). We have a parameter to disable this as a debugging option as a way for users to disable this, depending on their use case, and for us to help debug this further. Having this enabled seems like the lesser of to evils. Reviewed-by:
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Alex Deucher authored
Some users have reported flickerng with S/G display. We've tried extensively to reproduce and debug the issue on a wide variety of platform configurations (DRAM bandwidth, etc.) and a variety of monitors, but so far have not been able to. We disabled S/G display on a number of platforms to address this but that leads to failure to pin framebuffers errors and blank displays when there is memory pressure or no displays at all on systems with limited carveout (e.g., Chromebooks). Add a option to disable this as a debugging option as a way for users to disable this, depending on their use case, and for us to help debug this further. v2: fix typo Reviewed-by:
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Colin Ian King authored
The function name is being reported as dc_link_contruct when it is actually dc_link_construct_phy. Fix this by using %s and the __func__ for the function name. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
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Ye Xingchen authored
link_hwss.h is included more than once in link_dpms.c . Signed-off-by:
Ye Xingchen <ye.xingchen@zte.com.cn> Signed-off-by:
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Arnd Bergmann authored
When CONFIG_DRM_AMD_DC_DCN is disabled, the is_frl member is not defined: drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c: In function 'dp_active_dongle_validate_timing': drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c:126:66: error: 'const struct dc_dsc_config' has no member named 'is_frl' 126 | if (timing->flags.DSC && !timing->dsc_cfg.is_frl) | ^ Use the same #ifdef as the other references to this. Fixes: 54618888 ("drm/amd/display: break down dc_link.c") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Tom Rix authored
smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c:90:6: warning: symbol 'should_disable_otg' was not declared. Should it be static? should_disable_otg() is only used in dcn315_clk_mgr.c, so it should be static Signed-off-by:
Tom Rix <trix@redhat.com> Signed-off-by:
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Alex Deucher authored
Use fb_start/end for consistency with gmc code for non- XGMI systems, they are equivalent to vram_start/end. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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Alex Deucher authored
Need to cover both FB and AGP apertures. v2: fix missed gfxhub_v3_0_3.c Fixes: c6eafee0 ("Revert "Revert "drm/amdgpu/gmc11: enable AGP aperture""") Reviewed-by:
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Hamza Mahfooz authored
As made mention of in commit 4ea7fc09 ("drm/amd/display: Do not program interrupt status on disabled crtc"), we shouldn't program disabled crtcs. So, filter out disabled crtcs in dm_set_vupdate_irq() and dm_set_vblank(). Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Jane Jian authored
sriov does not need to init pptable from amdgpu driver we finish it from PF Signed-off-by:
Jane Jian <Jane.Jian@amd.com> Acked-by:
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JesseZhang authored
test ib function is not necessary on hw ring, so remove it. v2: squash in NULL check fix Signed-off-by:
JesseZhang <Jesse.Zhang@amd.com> Acked-by:
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Guilherme G. Piccoli authored
Currently amdgpu calls drm_sched_fini() from the fence driver sw fini routine - such function is expected to be called only after the respective init function - drm_sched_init() - was executed successfully. Happens that we faced a driver probe failure in the Steam Deck recently, and the function drm_sched_fini() was called even without its counter-part had been previously called, causing the following oops: amdgpu: probe of 0000:04:00.0 failed with error -110 BUG: kernel NULL pointer dereference, address: 0000000000000090 PGD 0 P4D 0 Oops: 0002 [#1] PREEMPT SMP NOPTI CPU: 0 PID: 609 Comm: systemd-udevd Not tainted 6.2.0-rc3-gpiccoli #338 Hardware name: Valve Jupiter/Jupiter, BIOS F7A0113 11/04/2022 RIP: 0010:drm_sched_fini+0x84/0xa0 [gpu_sched] [...] Call Trace: <TASK> amdgpu_fence_driver_sw_fini+0xc8/0xd0 [amdgpu] amdgpu_device_fini_sw+0x2b/0x3b0 [amdgpu] amdgpu_driver_release_kms+0x16/0x30 [amdgpu] devm_drm_dev_init_release+0x49/0x70 [...] To prevent that, check if the drm_sched was properly initialized for a given ring before calling its fini counter-part. Notice ideally we'd use sched.ready for that; such field is set as the latest thing on drm_sched_init(). But amdgpu seems to "override" the meaning of such field - in the above oops for example, it was a GFX ring causing the crash, and the sched.ready field was set to true in the ring init routine, regardless of the state of the DRM scheduler. Hence, we ended-up using sched.ops as per Christian's suggestion [0], and also removed the no_scheduler check [1]. [0] https://lore.kernel.org/amd-gfx/984ee981-2906-0eaf-ccec-9f80975cb136@amd.com/ [1] https://lore.kernel.org/amd-gfx/cd0e2994-f85f-d837-609f-7056d5fb7231@amd.com/ Fixes: 067f44c8 ("drm/amdgpu: avoid over-handle of fence driver fini in s3 test (v2)") Suggested-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by:
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Alex Deucher authored
Move variable declarations to where they are used. Fixes a segfault on smu7 V0 structures where some tables don't exist. Cc: Evan Quan <evan.quan@amd.com> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2388 Fixes: b1a9557a ("drm/amd/pm: fulfill powerplay peak profiling mode shader/memory clock settings") Reviewed-by:
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- 08 Feb, 2023 17 commits
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Friedrich Vock authored
The pid field corresponds to the result of gettid() in userspace. However, userspace cannot reliably attribute PTE events to processes with just the thread id. This patch allows userspace to easily attribute PTE update events to specific processes by comparing this field with the result of getpid(). For attributing events to specific threads, the thread id is also contained in the common fields of each trace event. Reviewed-by:
Friedrich Vock <friedrich.vock@gmx.de> Signed-off-by:
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Kent Russell authored
These can support unique_id, so create the sysfs file for them Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
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Evan Quan authored
This can suppress the warning caused by version mismatch. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along the following: - FW 0.0.153.0 - Code re-organize for dc_link.c - Bug fixes on rotation, DRR and more Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Jingwen Zhu authored
[Why] This is a workaround for an dcn3.15 hang that happens if otg dispclk is ramped while otg is on and stream enc is off. But this w/a should not trigger when we have a dig active. [How] Avoid disable otg when dig was disabled. [Note] Reapplying commit b07bb766 ("drm/amd/display: avoid disable otg when dig was disabled") which was incorrectly reverted. Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Acked-by:
Jingwen Zhu <Jingwen.Zhu@amd.com> Signed-off-by:
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Evan Quan authored
This can suppress the warning caused by version mismatch. Signed-off-by:
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Evan Quan authored
Add missing GetPptLimit message mapping. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Arnd Bergmann authored
A conversion from 'bool' to 'enum odm_combine_mode' was incomplete, and gcc warns about this with many instances of display/dc/dml/dcn20/display_mode_vba_20.c:3899:44: warning: implicit conversion from 'enum <anonymous>' to 'enum odm_combine_mode' [-Wenum-conversion] 3899 | locals->ODMCombineEnablePerState[i][k] = false; Change the ones that we get a warning for, using the same numerical values to leave the behavior unchanged. Fixes: 5fc11598 ("drm/amd/display: expand dml structs") Link: https://lore.kernel.org/all/20201026210039.3884312-3-arnd@kernel.org/ Link: https://lore.kernel.org/all/20210927100659.1431744-1-arnd@kernel.org/Signed-off-by:
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Randy Dunlap authored
The path for the "mod_info_packet.h" header file is incomplete, so add its location to the header search path in the amdgpu Makefile. See on ARCH=alpha (275 times in one build). In file included from ../drivers/gpu/drm/amd/amdgpu/amdgpu.h:90, from ../drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:43: ../drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.h:62:10: fatal error: mod_info_packet.h: No such file or directory 62 | #include "mod_info_packet.h" | ^~~~~~~~~~~~~~~~~~~ compilation terminated. Fixes: 5b49da02 ("drm/amd/display: Enable Freesync over PCon") Signed-off-by:Randy Dunlap <rdunlap@infradead.org> Cc: Signed-off-by: Sung Joon Kim <sungkim@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by:
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Kent Russell authored
This looks like a standard copy/paste mistake. Replace the incorrect serial_number references with product_name and product_model Signed-off-by:
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Melissa Wen authored
Cursor gets clipped off in the middle of the screen with hw rotation 180. Fix a miscalculation of cursor offset when it's placed near the edges in the pipe split case. Cursor bugs with hw rotation were reported on AMD issue tracker: https://gitlab.freedesktop.org/drm/amd/-/issues/2247 The issues on rotation 270 was fixed by: https://lore.kernel.org/amd-gfx/20221118125935.4013669-22-Brian.Chang@amd.com/ that partially addressed the rotation 180 too. So, this patch is the final bits for rotation 180. Reported-by:
Xaver Hugl <xaver.hugl@gmail.com> Reviewed-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Anthony Koo authored
[Why&How] - Reduce reserved size from 9 to 8 dwords to reduce structure size and allow the union dmub_rb_cmd to fit into max 64-bytes cmd size Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Hans de Goede authored
Remove CONFI_BACKLIGHT_CLASS_DEVICE ifdef that was accidently introduced back. Reviewed-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Wenjing Liu authored
[why] dc_link contains over 30k line of code, the decision is to break it down to files residing in link folder based on functionality. This change is the last break down change which will remove dc_link.c file after everything is broken down. [how] Move remaining dc_link.c functions into link_detection, link_dpms, link_validation, link_resource, and link_fpga and remove dc_link. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Leo (Hanghong) Ma authored
[Why && How] Add support to read manufacturer OUI and device id from HDMI SCDC. Reviewed-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Fix the null pointer dererefence error when rotating the monitor on a DCN32 variant, which causes a call trace like: [ 42.469548] RIP: 0010:dcn20_program_front_end_for_ctx.cold+0x68/0x435 [amdgpu] [ 42.477140] Code: c1 4c 01 e8 48 8b b0 f0 01 00 00 e8 b6 1c 4c f9 42 f6 84 2b a0 0a 00 00 02 74 30 4d 03 ac 24 68 04 00 00 49 8b 85 f0 01 00 00 <83> b8 50 06 00 00 02 75 18 49 8b bd e0 02 00 00 48 8b 07 48 8b 40 [ 42.496225] RSP: 0018:ffffaf744326f6a0 EFLAGS: 00010282 [ 42.501539] RAX: 0000000000000000 RBX: ffff948765180000 RCX: 0000000000000000 [ 42.508797] RDX: 0000000000000000 RSI: ffffffffbaea5329 RDI: 00000000ffffffff [ 42.516055] RBP: ffff948701674400 R08: 0000000000000000 R09: ffffaf744326f538 [ 42.523312] R10: 0000000000000003 R11: ffff948a1d33ffe8 R12: ffff948708700000 [ 42.530569] R13: ffff94876e901180 R14: 0000000000000002 R15: 0000000000000001 [ 42.537825] FS: 00007f1c7c04a5c0(0000) GS:ffff948a05a80000(0000) knlGS:0000000000000000 [ 42.546055] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 42.551898] CR2: 0000000000000650 CR3: 0000000127dd6000 CR4: 00000000003506e0 [ 42.559155] Call Trace: [ 42.561645] <TASK> [ 42.563782] commit_planes_for_stream+0x8b1/0x1410 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46] [ 42.573298] dc_update_planes_and_stream+0x3f9/0x9f0 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46] [ 42.582986] amdgpu_dm_atomic_commit_tail+0x19be/0x3270 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46] [ 42.592944] ? vsnprintf+0x35e/0x550 [ 42.596593] commit_tail+0x94/0x130 [ 42.600146] drm_atomic_helper_commit+0x112/0x140 [ 42.604931] drm_atomic_commit+0x96/0xc0 [ 42.608922] ? drm_plane_get_damage_clips.cold+0x1c/0x1c [ 42.614326] drm_mode_atomic_ioctl+0x97b/0xb90 [ 42.618848] ? drm_atomic_set_property+0xb40/0xb40 [ 42.623633] drm_ioctl_kernel+0xc9/0x170 [ 42.627694] drm_ioctl+0x22f/0x410 [ 42.631157] ? drm_atomic_set_property+0xb40/0xb40 [ 42.636031] amdgpu_drm_ioctl+0x4a/0x80 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46] [ 42.644537] __x64_sys_ioctl+0x90/0xd0 [ 42.648355] do_syscall_64+0x5b/0x80 [ 42.651992] ? do_syscall_64+0x67/0x80 [ 42.655808] ? exit_to_user_mode_prepare+0x1e/0x140 [ 42.660773] entry_SYSCALL_64_after_hwframe+0x63/0xcd [ 42.665913] RIP: 0033:0x7f1c7f31aaff [ 42.669550] Code: 00 48 89 44 24 18 31 c0 48 8d 44 24 60 c7 04 24 10 00 00 00 48 89 44 24 08 48 8d 44 24 20 48 89 44 24 10 b8 10 00 00 00 0f 05 <41> 89 c0 3d 00 f0 ff ff 77 1f 48 8b 44 24 18 64 48 2b 04 25 28 00 [ 42.688635] RSP: 002b:00007fff29eca1a0 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 42.696334] RAX: ffffffffffffffda RBX: 00007fff29eca250 RCX: 00007f1c7f31aaff [ 42.703591] RDX: 00007fff29eca250 RSI: 00000000c03864bc RDI: 0000000000000009 [ 42.710848] RBP: 00000000c03864bc R08: 000000000000000e R09: 000000000000000e [ 42.718104] R10: 0000000000000007 R11: 0000000000000246 R12: 00005643f0991d70 [ 42.725361] R13: 0000000000000009 R14: 00005643f22d0c50 R15: 00005643f0a74550 [ 42.732621] </TASK> Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Acked-by:
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Wesley Chalmers authored
[WHY] DRR and Pipe cannot be updated on the same frame, or else underflow will occur. Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by:
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