- 10 Sep, 2020 13 commits
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Lorenzo Bianconi authored
Remove mvneta_stats from mvneta_swbm_rx_frame signature since now stats are accounted in mvneta_run_xdp routine Signed-off-by:
Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by:
David S. Miller <davem@davemloft.net>
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David S. Miller authored
Jakub Kicinski says: ==================== netpoll: make sure napi_list is safe for RCU traversal This series is a follow-up to the fix in commit 96e97bc0 ("net: disable netpoll on fresh napis"). To avoid any latent race conditions convert dev->napi_list to a proper RCU list. We need minor restructuring because it looks like netif_napi_del() used to be idempotent, and it may be quite hard to track down everyone who depends on that. ==================== Signed-off-by:
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Jakub Kicinski authored
netpoll needs to traverse dev->napi_list under RCU, make sure it uses the right iterator and that removal from this list is handled safely. Signed-off-by:
Jakub Kicinski <kuba@kernel.org> Signed-off-by:
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Jakub Kicinski authored
To RCUify napi->dev_list we need to replace list_del_init() with list_del_rcu(). There is no _init() version for RCU for obvious reasons. Up until now netif_napi_del() was idempotent so to make sure it remains such add a bit which is set when NAPI is listed, and cleared when it removed. Since we don't expect multiple calls to netif_napi_add() to be correct, add a warning on that side. Now that napi_hash_add / napi_hash_del are only called by napi_add / del we can actually steal its bit. We just need to make sure hash node is initialized correctly. Signed-off-by:
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Jakub Kicinski authored
We allow drivers to call napi_hash_del() before calling netif_napi_del() to batch RCU grace periods. This makes the API asymmetric and leaks internal implementation details. Soon we will want the grace period to protect more than just the NAPI hash table. Restructure the API and have drivers call a new function - __netif_napi_del() if they want to take care of RCU waits. Note that only core was checking the return status from napi_hash_del() so the new helper does not report if the NAPI was actually deleted. Some notes on driver oddness: - veth observed the grace period before calling netif_napi_del() but that should not matter - myri10ge observed normal RCU flavor - bnx2x and enic did not actually observe the grace period (unless they did so implicitly) - virtio_net and enic only unhashed Rx NAPIs The last two points seem to indicate that the calls to napi_hash_del() were a left over rather than an optimization. Regardless, it's easy enough to correct them. This patch may introduce extra synchronize_net() calls for interfaces which set NAPI_STATE_NO_BUSY_POLL and depend on free_netdev() to call netif_napi_del(). This seems inevitable since we want to use RCU for netpoll dev->napi_list traversal, and almost no drivers set IFF_DISABLE_NETPOLL. Signed-off-by:
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David S. Miller authored
Jakub Kicinski says: ==================== mlx4: avoid devlink port type not set warnings This small set addresses the issue of mlx4 potentially not setting devlink port type when Ethernet or IB driver is not built, but port has that type. v2: - add patch 1 ==================== Signed-off-by: -
Jakub Kicinski authored
Even tho mlx4_core registers the devlink ports, it's mlx4_en and mlx4_ib which set their type. In situations where one of the two is not built yet the machine has ports of given type we see the devlink warning from devlink_port_type_warn() trigger. Having ports of a type not supported by the kernel may seem surprising, but it does occur in practice - when the unsupported port is not plugged in to a switch anyway users are more than happy not to see it (and potentially allocate any resources to it). Set the type in mlx4_core if type-specific driver is not built. Signed-off-by:
Tariq Toukan <tariqt@mellanox.com> Signed-off-by:
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Jakub Kicinski authored
Following change will add support for a corner case where we may not have a netdev to pass to devlink_port_type_eth_set() but we still want to set port type. This is definitely a corner case, and drivers should not normally pass NULL netdev - print a warning message when this happens. Sadly for other port types (ib) switches don't have a device reference, the way we always do for Ethernet, so we can't put the warning in __devlink_port_type_set(). Signed-off-by:
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Lorenzo Bianconi authored
In order to easily change the rx buffer size, rely on MVNETA_MAX_RX_BUF_SIZE instead of PAGE_SIZE in mvneta_swbm_rx_frame routine for rx buffer split. Currently this is not an issue since we set MVNETA_MAX_RX_BUF_SIZE to PAGE_SIZE - MVNETA_SKB_PAD but it is a good to have to configure a different rx buffer size. Signed-off-by:
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David S. Miller authored
Paul Davey says: ==================== Allow more than 255 IPv4 multicast interfaces Currently it is not possible to use more than 255 multicast interfaces for IPv4 due to the format of the igmpmsg header which only has 8 bits available for the VIF ID. There is space available in the igmpmsg header to store the full VIF ID in the form of an unused byte following the VIF ID field. There is also enough space for the full VIF ID in the Netlink cache notifications, however the value is currently taken directly from the igmpmsg header and has thus already been truncated. Adding the high byte of the VIF ID into the unused3 byte of igmpmsg allows use of more than 255 IPv4 multicast interfaces. The full VIF ID is also available in the Netlink notification by assembling it from both bytes from the igmpmsg. Additionally this reveals a deficiency in the Netlink cache report notifications, they lack any means for differentiating cache reports relating to different multicast routing tables. This is easily resolved by adding the multicast route table ID to the cache reports. changes in v2: - Added high byte of VIF ID to igmpmsg struct replacing unused3 member. - Assemble VIF ID in Netlink notification from both bytes in igmpmsg header. ==================== Signed-off-by: -
Paul Davey authored
Insert the full 16 bit VIF ID into ipmr Netlink cache reports. The VIF_ID attribute has 32 bits of space so can store the full VIF ID extracted from the high and low byte fields in the igmpmsg. Signed-off-by:
Paul Davey <paul.davey@alliedtelesis.co.nz> Signed-off-by:
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Paul Davey authored
Use the unused3 byte in struct igmpmsg to hold the high 8 bits of the VIF ID. If using more than 255 IPv4 multicast interfaces it is necessary to have access to a VIF ID for cache reports that is wider than 8 bits, the VIF ID present in the igmpmsg reports sent to mroute_sk was only 8 bits wide in the igmpmsg header. Adding the high 8 bits of the 16 bit VIF ID in the unused byte allows use of more than 255 IPv4 multicast interfaces. Signed-off-by:
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Paul Davey authored
Insert the multicast route table ID as a Netlink attribute to Netlink cache report notifications. When multiple route tables are in use it is necessary to have a way to determine which route table a given cache report belongs to when receiving the cache report. Signed-off-by:
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- 09 Sep, 2020 27 commits
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Florian Fainelli authored
We already maintain an array of VLANs used by the switch so we can simply iterate over it to report the occupancy via devlink. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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David S. Miller authored
Russell King says: ==================== Marvell PP2.2 PTP support This series adds PTP support for PP2.2 hardware to the mvpp2 driver. Tested on the Macchiatobin eth1 port. Note that on the Macchiatobin, eth0 uses a separate TAI block from eth1, and there is no hardware synchronisation between the two. ==================== Signed-off-by: -
Russell King authored
Add support for timestamping transmit packets. We allocate SYNC messages to queue 1, every other message to queue 0. Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by:
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Russell King authored
Add support for receive timestamping. When enabled, the hardware adds a timestamp into the receive queue descriptor for all received packets with no filtering. Hence, we can only support NONE or ALL receive filter modes. The timestamp in the receive queue contains two bit sof seconds and the full nanosecond timestamp. This has to be merged with the remainder of the seconds from the TAI clock to arrive at a full timestamp before we can convert it to a ktime for the skb hardware timestamp field. Signed-off-by:
Richard Cochran <richardcochran@gmail.com> Signed-off-by:
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Russell King authored
Add support for the TAI block in the mvpp2.2 hardware. Acked-by:
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Russell King authored
Check the first level interrupt status registers to determine how to further process the port interrupt. We will need this to know whether to invoke the link status processing and/or the PTP processing for both XLG and GMAC. Reviewed-by:
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Russell King authored
The link interrupt is used for way more than just the link status; it comes from a collection of units to do with the port. The Marvell documentation describes the interrupt as "GOP port X interrupt". Since we are adding PTP support, and the PTP interrupt uses this, rename it to be more inline with the documentation. This interrupt is also mis-named in the DT binding, but we leave that alone. Reviewed-by:
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Russell King authored
The "link status" interrupt is used for more than just link status. Restructure mvpp2_link_status_isr() so we can add additional handling. Reviewed-by:
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David S. Miller authored
Parav Pandit says: ==================== devlink show controller number Currently a devlink instance that supports an eswitch handles eswitch ports of two type of controllers. (1) controller discovered on same system where eswitch resides. This is the case where PCI PF/VF of a controller and devlink eswitch instance both are located on a single system. (2) controller located on external system. This is the case where a controller is plugged in one system and its devlink eswitch ports are located in a different system. In this case devlink instance of the eswitch only have access to ports of the controller. However, there is no way to describe that a eswitch devlink port belongs to which controller (mainly which external host controller). This problem is more prevalent when port attribute such as PF and VF numbers are overlapping between multiple controllers of same eswitch. Due to this, for a specific switch_id, unique phys_port_name cannot be constructed for such devlink ports. This short series overcomes this limitation by defining two new attributes. (a) external: Indicates if port belongs to external controller (b) controller number: Indicates a controller number of the port Based on this a unique phys_port_name is prepared using controller number. phys_port_name construction using unique controller number is only applicable to external controller ports. This ensures that for non smartnic usecases where there is no external controller, phys_port_name stays same as before. Patch summary: Patch-1 Added mlx5 driver to read controller number Patch-2 Adds the missing comment for the port attributes Patch-3 Move structure comments away from structure fields Patch-4 external attribute added for PCI port flavours Patch-5 Add controller number Patch-6 Use controller number to build phys_port_name --- Changelog: v2->v3: - Updated diagram to get rid of controller 'A' and 'B' - Kept ports of single controller together in diagram - Updated diagram for pf1's VF and SF and its ports v1->v2: - Added text diagram of multiple controllers - Updated example for a VF - Addressed comments from Jiri and Jakub - Moved controller number attribute to PCI port flavours This enables to better, hirerchical view with controller and its PF, VF numbers - Split 'external' and 'controller number' attributes as two different attributes - Merged mlx5_core driver to avoid compiliation break ==================== Acked-by: -
Parav Pandit authored
Now that controller number attribute is available, use it when building phsy_port_name for external controller ports. An example devlink port and representor netdev name consist of controller annotation for external controller with controller number = 1, for a VF 1 of PF 0: $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev ens2f0c1pf0vf1 flavour pcivf controller 1 pfnum 0 vfnum 1 external true splittable false function: hw_addr 00:00:00:00:00:00 $ devlink port show pci/0000:06:00.0/2 -jp { "port": { "pci/0000:06:00.0/2": { "type": "eth", "netdev": "ens2f0c1pf0vf1", "flavour": "pcivf", "controller": 1, "pfnum": 0, "vfnum": 1, "external": true, "splittable": false, "function": { "hw_addr": "00:00:00:00:00:00" } } } } Controller number annotation is skipped for non external controllers to maintain backward compatibility. Signed-off-by:Parav Pandit <parav@nvidia.com> Reviewed-by:
Jiri Pirko <jiri@nvidia.com> Signed-off-by:
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Parav Pandit authored
A devlink port may be for a controller consist of PCI device. A devlink instance holds ports of two types of controllers. (1) controller discovered on same system where eswitch resides This is the case where PCI PF/VF of a controller and devlink eswitch instance both are located on a single system. (2) controller located on external host system. This is the case where a controller is located in one system and its devlink eswitch ports are located in a different system. When a devlink eswitch instance serves the devlink ports of both controllers together, PCI PF/VF numbers may overlap. Due to this a unique phys_port_name cannot be constructed. For example in below such system controller-0 and controller-1, each has PCI PF pf0 whose eswitch ports can be present in controller-0. These results in phys_port_name as "pf0" for both. Similar problem exists for VFs and upcoming Sub functions. An example view of two controller systems: --------------------------------------------------------- | | | --------- --------- ------- ------- | ----------- | | vf(s) | | sf(s) | |vf(s)| |sf(s)| | | server | | ------- ----/---- ---/----- ------- ---/--- ---/--- | | pci rc |=== | pf0 |______/________/ | pf1 |___/_______/ | | connect | | ------- ------- | ----------- | | controller_num=1 (no eswitch) | ------|-------------------------------------------------- (internal wire) | --------------------------------------------------------- | devlink eswitch ports and reps | | ----------------------------------------------------- | | |ctrl-0 | ctrl-0 | ctrl-0 | ctrl-0 | ctrl-0 |ctrl-0 | | | |pf0 | pf0vfN | pf0sfN | pf1 | pf1vfN |pf1sfN | | | ----------------------------------------------------- | | |ctrl-1 | ctrl-1 | ctrl-1 | ctrl-1 | ctrl-1 |ctrl-1 | | | |pf1 | pf1vfN | pf1sfN | pf1 | pf1vfN |pf0sfN | | | ----------------------------------------------------- | | | | | | --------- --------- ------- ------- | | | vf(s) | | sf(s) | |vf(s)| |sf(s)| | | ------- ----/---- ---/----- ------- ---/--- ---/--- | | | pf0 |______/________/ | pf1 |___/_______/ | | ------- ------- | | | | local controller_num=0 (eswitch) | --------------------------------------------------------- An example devlink port for external controller with controller number = 1 for a VF 1 of PF 0: $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev ens2f0pf0vf1 flavour pcivf controller 1 pfnum 0 vfnum 1 external true splittable false function: hw_addr 00:00:00:00:00:00 $ devlink port show pci/0000:06:00.0/2 -jp { "port": { "pci/0000:06:00.0/2": { "type": "eth", "netdev": "ens2f0pf0vf1", "flavour": "pcivf", "controller": 1, "pfnum": 0, "vfnum": 1, "external": true, "splittable": false, "function": { "hw_addr": "00:00:00:00:00:00" } } } } Signed-off-by: -
Parav Pandit authored
A devlink eswitch port may represent PCI PF/VF ports of a controller. A controller either located on same system or it can be an external controller located in host where such NIC is plugged in. Add the ability for driver to specify if a port is for external controller. Use such flag in the mlx5_core driver. An example of an external controller having VF1 of PF0 belong to controller 1. $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev ens2f0pf0vf1 flavour pcivf pfnum 0 vfnum 1 external true splittable false function: hw_addr 00:00:00:00:00:00 $ devlink port show pci/0000:06:00.0/2 -jp { "port": { "pci/0000:06:00.0/2": { "type": "eth", "netdev": "ens2f0pf0vf1", "flavour": "pcivf", "pfnum": 0, "vfnum": 1, "external": true, "splittable": false, "function": { "hw_addr": "00:00:00:00:00:00" } } } } Signed-off-by: -
Parav Pandit authored
To add more fields to the PCI PF and VF port attributes, follow standard structure comment format. Signed-off-by:
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Parav Pandit authored
Add comment block for physical, PF and VF port attributes. Signed-off-by:
Roi Dayan <roid@nvidia.com> Signed-off-by:
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Parav Pandit authored
ECPF supports one external host controller. Read controller number from the device. Signed-off-by:
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Zhang Changzhong authored
Because clk_prepare_enable() and clk_disable_unprepare() already checked NULL clock parameter, so the additional checks are unnecessary, just remove them. Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Zhang Changzhong <zhangchangzhong@huawei.com> Signed-off-by:
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Zhang Changzhong authored
Because clk_prepare_enable() and clk_disable_unprepare() already checked NULL clock parameter, so the additional checks are unnecessary, just remove them. Reported-by:
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David S. Miller authored
Marco Felsch says: ==================== SMSC: Cleanups and clock setup this small series cleans the smsc-phy code a bit and adds the support to specify the phy clock source. Adding the phy clock source support is also the main purpose of this series. Each file has its own changelog. Thanks a lot to Florian and Andrew for reviewing it. ==================== Signed-off-by: -
Marco Felsch authored
Don't reset the phy without respect to the PHY library state machine because this breaks the phy IRQ mode. The same behaviour can be archived now by specifying the refclk. Signed-off-by:
Marco Felsch <m.felsch@pengutronix.de> Reviewed-by:
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Marco Felsch authored
Add support to specify the clock provider for the PHY refclk and don't rely on 'magic' host clock setup. [1] tried to address this by introducing a flag and fixing the corresponding host. But this commit breaks the IRQ support since the irq setup during .config_intr() is thrown away because the reset comes from the side without respecting the current PHY state within the PHY library state machine. Furthermore the commit fixed the problem only for FEC based hosts other hosts acting like the FEC are not covered. This commit goes the other way around to address the bug fixed by [1]. Instead of resetting the device from the side every time the refclk gets (re-)enabled it requests and enables the clock till the device gets removed. Now the PHY library is the only place where the PHY gets reset to respect the PHY library state machine. [1] commit 7f64e5b1 ("net: phy: smsc: LAN8710/20: add PHY_RST_AFTER_CLK_EN flag") Signed-off-by:
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Marco Felsch authored
Add support to specify the reference clock for the phy. Signed-off-by:
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Marco Felsch authored
Exit the driver specific config_init hook early if energy detection is disabled. We can do this because we don't need to clear the interrupt status here. Clearing the status should be removed anyway since this is handled by the phy_enable_interrupts(). Signed-off-by:
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Marco Felsch authored
Don't enable the interrupt if the platform disable the energy detection by "smsc,disable-energy-detect". Signed-off-by:
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Wang Hai authored
Rename ptp to ptp_info. Fix W=1 compile warnings (invalid kerneldoc): drivers/net/ethernet/cavium/common/cavium_ptp.c:94: warning: Excess function parameter 'ptp' description in 'cavium_ptp_adjfine' drivers/net/ethernet/cavium/common/cavium_ptp.c:141: warning: Excess function parameter 'ptp' description in 'cavium_ptp_adjtime' drivers/net/ethernet/cavium/common/cavium_ptp.c:163: warning: Excess function parameter 'ptp' description in 'cavium_ptp_gettime' drivers/net/ethernet/cavium/common/cavium_ptp.c:185: warning: Excess function parameter 'ptp' description in 'cavium_ptp_settime' drivers/net/ethernet/cavium/common/cavium_ptp.c:208: warning: Excess function parameter 'ptp' description in 'cavium_ptp_enable' Reported-by:
Wang Hai <wanghai38@huawei.com> Signed-off-by:
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Ayush Sawal authored
As ch_ipsec was removed without clearing xfrmdev_ops and netdev feature(esp-hw-offload). When a recalculation of netdev feature is triggered by changing tls feature(tls-hw-tx-offload) from user request, it causes a page fault due to absence of valid xfrmdev_ops. Fixes: 6dad4e8a ("chcr: Add support for Inline IPSec") Signed-off-by:
Ayush Sawal <ayush.sawal@chelsio.com> Acked-by:
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David S. Miller authored
Paul Barker says: ==================== ksz9477 dsa switch driver improvements These changes were made while debugging the ksz9477 driver for use on a custom board which uses the ksz9893 switch supported by this driver. The patches have been runtime tested on top of Linux 5.8.4, I couldn't runtime test them on top of 5.9-rc3 due to unrelated issues. They have been build tested on top of net-next. These changes can also be pulled from: https://gitlab.com/pbarker.dev/staging/linux.git tag: for-net-next/ksz-v3_2020-09-09 Changes from v2: * Fixed incorrect type in assignment error. Reported-by:
kernel test robot <lkp@intel.com> Changes from v1: * Rebased onto net-next. * Dropped unnecessary `#include <linux/printk.h>`. * Instead of printing the phy mode in `ksz9477_port_setup()`, modify the existing print in `ksz9477_config_cpu_port()` to always produce output and to be more clear. ==================== Signed-off-by:
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Paul Barker authored
The datasheet for the ksz9893 and ksz9477 switches recommend waiting at least 100us after the de-assertion of reset before trying to program the device through any interface. Also switch the existing msleep() call to usleep_range() as recommended in Documentation/timers/timers-howto.rst. The 2ms range used here is somewhat arbitrary, as long as the reset is asserted for at least 10ms we should be ok. Signed-off-by:
Paul Barker <pbarker@konsulko.com> Reviewed-by:
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