- 26 Feb, 2021 18 commits
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Alex Deucher authored
For each asic family. Will be used to populate tables for the new INFO ioctl query. v2: add max_pixels_per_frame to handle the portrait case v3: fix copy paste typos Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> (v1) Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This will be used by a new INFO ioctl query to fetch the decode and encode capabilities from the kernel driver rather than hardcoding them in mesa. This gives us more fine grained control of capabilities using information that is only availabl in the kernel (e.g., platform limitations or bandwidth restrictions). v2: reorder the codecs to better align with mesa v3: add max_pixels_per_frame to handle the portrait case Reviewed-by:
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Aurabindo Pillai authored
[Why] A seamless transition between modes can be performed if the new incoming mode has the same timing parameters as the optimized mode on a display with a variable vtotal min/max. Smooth video playback usecases can be enabled with this seamless transition by switching to a new mode which has a refresh rate matching the video. [How] Skip full modeset if userspace requested a compatible freesync mode which only differs in the front porch timing from the current mode. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why] While possible for userspace to create and add custom mode based off the optimized mode for the connected display which differs only in front porch timing, this patch set adds a list of common video modes in advance. The list of common video refresh rates is small, well known and the optimized mode has specific requirements to be able to enable HW frame doubling and tripling so it makes most sense to create the modes that video players will need in advance. The optimized mode matches the preferred mode resolution but has the highest refresh rate available to enable the largest front porch extension. [How] Find the optimized mode and store it on the connector so we can check it later during our optimized modeset. Prepopulate the mode list with a list of common video mades based on the optimized mode (but with a longer front porch) if the panel doesn't support a variant of the mode natively. Signed-off-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why] This option shall be opt-in by default since it is a temporary solution until long term solution is agreed upon which may require userspace interface changes. This feature give the user a seamless experience when freesync aware programs (media players for instance) switches to a compatible freesync mode when playing videos. Enabling this feature also have the potential side effect of causing higher power consumption due to running a mode with lower resolution and base clock frequency with the highest base clock supported on the monitor as per its advertised modes. There has been precedent of manufacturing modes in the kernel. In AMDGPU, the existing usage are for common modes and scaling modes. Other driver have a similar approach as well. [How] Adds a module parameter to enable freesync video mode modeset optimization. Enabling this mode allows the driver to skip a full modeset when a freesync compatible mode is requested by the userspace. This parameter will also add some additional modes that are within the connected monitor's VRR range corresponding to common video modes, which media players can use for a seamless experience while making use of freesync. Signed-off-by:
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Ramesh Errabolu authored
Currently callers have to provide handle of amdgpu_device, which is not used by the implementation. It is unlikely this parameter will become useful in future, thus removing it v2: squash in unused variable fix Reviewed-by:
Ramesh Errabolu <Ramesh.Errabolu@amd.com> Signed-off-by:
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Jingwen Chen authored
Move gpu_reset_counter after drm_sched_stop to avoid race condition caused by job submitted between reset_count +1 and drm_sched_stop. Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by:
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Darren Powell authored
v3: updated to include new clocks od_vddgfx_offset, od_cclk Context mismatch with revision v3 to patch 0003 Modified Functions smu_sys_set_pp_table() - modifed signature to match Powerplay API set_pp_table smu_force_performance_level() - modifed arg0 to match Powerplay API force_performance_level smu_od_edit_dpm_table() - modifed arg0 to match Powerplay API odn_edit_dpm_table Other Changes smu_od_edit_dpm_table() - removed call to task(READJUST_POWER_STATE) after COMMIT_TABLE, now handled in calling function amdgpu_set_power_dpm_force_performance_level() - now checks thermal for swsmu systems before trying to change level amdgpu_set_pp_od_clk_voltage() - now attempts to set fine_grain_clock_vol before swsmu edit dpm table Signed-off-by:Darren Powell <darren.powell@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Darren Powell authored
v2: fix errors and warnings flagged by checkpatch v3: Context mismatch with revision v3 to patch 0003 New Functions smu_get_mclk - implementation of the Powerplay API function get_mclk smu_get_sclk - implementation of the Powerplay API function get_sclk smu_handle_dpm_task - implementation of the Powerplay API function dispatch_tasks Modified Functions smu_dpm_set_power_gate - - modifed arg0 to match Powerplay API set_powergating_by_smu Other Changes removed special smu handling in dpm functions and called through Powerplay API call to smu_dpm_set_power_gate via Powerplay API now locks mutex for UVD and VCE Signed-off-by:
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Darren Powell authored
v3: updated to include new clocks vclk, dclk, od_vddgfx_offset, od_cclk Added forward declaration for function smu_force_smuclk_levels to resolve clash with other commits Resolved context clashes with other commits and v3 updates to patches 0003, 0004 v2: fix errors flagged by checkpatch New Functions smu_bump_power_profile_mode() - changes profile mode assuming calling function already has mutex smu_force_ppclk_levels() - accepts Powerplay enum pp_clock_type to specify clock to change smu_print_ppclk_levels() - accepts Powerplay enum pp_clock_type to request clock levels amdgpu_get_pp_dpm_clock() - accepts Powerplay enum pp_clock_type to request clock levels and allows all the amdgpu_get_pp_dpm_$CLK functions to have a single codepath amdgpu_set_pp_dpm_clock() - accepts Powerplay enum pp_clock_type to set clock levels and allows all the amdgpu_set_pp_dpm_$CLK functions to have a single codepath Modified Functions smu_force_smuclk_levels - changed function name to make clear difference to smu_force_ppclk_levels smu_force_ppclk_levels() - modifed signature to implement Powerplay API force_clock_level - calls smu_force_smuclk_levels smu_print_smuclk_levels - changed function name to make clear difference to smu_print_ppclk_levels smu_print_ppclk_levels() - modifed signature to implement Powerplay API force_clock_level - calls smu_print_smuclk_levels smu_sys_get_gpu_metrics - modifed arg0 to match Powerplay API get_gpu_metrics smu_get_power_profile_mode - modifed arg0 to match Powerplay API get_power_profile_mode smu_set_power_profile_mode - modifed arg0 to match Powerplay API set_power_profile_mode - removed arg lock_needed, mutex always locked, internal functions can call smu_bump if they already hold lock smu_switch_power_profile - now calls smu_bump as already holds mutex lock smu_adjust_power_state_dynamic - now calls smu_bump as already holds mutex lock amdgpu_get_pp_od_clk_voltage - uses smu_print_ppclk_levels amdgpu_{set,get}_pp_dpm_$CLK - replace logic with call helper function amdgpu_{set,get}_pp_dpm_clock() CLK ={sclk, mclk, socclk, fclk, dcefclk, pci, vclkd, dclk} Other Changes added 5 smu Powerplay functions to swsmu_dpm_funcs removed special smu handling in pm functions and called through Powerplay API Signed-off-by: -
Darren Powell authored
v2: add comment to highlight assignment that changes uint32_t value to int fix errors flagged by checkpatch.pl New Functions smu_get_baco_capability() - Implement Powerplay API get_asic_baco_capability smu_baco_set_state() - Implement Powerplay API set_asic_baco_state Modified Functions smu_read_sensor() - modifed signature to match Powerplay API read_sensor Other Changes added 3 above smu Powerplay functions to swsmu_dpm_funcs removed special smu handling in 5 dpm functions and called through Powerplay API Signed-off-by: -
Darren Powell authored
v2: remove check for error during swsmu amdgpu_dpm_get_pp_num_states() call to match previous powerplay behaviour v3: removed smu implementation of powerplay get_power_limit Resolved context clashes with other commits Modified Files smu_set_power_limit() - modifed arg0 to match Powerplay API set_power_limit smu_sys_get_pp_table() - modifed signature to match Powerplay API get_pp_table smu_get_power_num_states() - modifed arg0 to match Powerplay API get_pp_num_states smu_get_current_power_state() - modifed arg0 to match Powerplay API get_current_power_state smu_sys_get_pp_feature_mask() - modifed signature to match Powerplay API get_ppfeature_status smu_sys_set_pp_feature_mask() - modifed arg0 to match Powerplay API set_ppfeature_status Other Changes added 6 above smu Powerplay functions to swsmu_dpm_funcs removed special smu handling of above functions and called through Powerplay API Signed-off-by: -
Darren Powell authored
v2: changed error return value of smu_get_fan_control_mode to AMD_FAN_CTRL_NONE fixed type in amdgpu_hwmon_get_pwm1_enable() print statement fixed indent flagged by checkpatch.pl Modified Functions smu_set_fan_speed_rpm() - modifed arg0 to match Powerplay API set_fan_speed_rpm smu_get_fan_control_mode() - modifed signature to match Powerplay API get_fan_control_mode smu_set_fan_control_mode() - modifed signature to match Powerplay API set_fan_control_mode smu_get_fan_speed_percent() - modifed signature to match Powerplay API get_fan_speed_percent smu_set_fan_speed_percent() - modifed signature to match Powerplay API set_fan_speed_percent smu_get_fan_speed_rpm() - modifed arg0 to match Powerplay API get_fan_speed_rpm Other Changes added 6 above smu fan Powerplay functions to swsmu_dpm_funcs removed special smu handling of above functions and called through Powerplay API Signed-off-by: -
Darren Powell authored
Modified Functions smu_set_xgmi_pstate() - modifed arg0 to match Powerplay API set_xgmi_pstate smu_mode2_reset() - modifed arg0 to match Powerplay API asic_reset_mode_2 smu_switch_power_profile() - modifed arg0 to match Powerplay API switch_power_profile smu_set_mp1_state() - modifed arg0 to match Powerplay API set_mp1_state smu_set_df_cstate() - modifed arg0 to match Powerplay API set_df_cstate smu_enable_mgpu_fan_boost() - modifed arg0 to match Powerplay API enable_mgpu_fan_boost Other Changes added above smu reset Powerplay functions to swsmu_dpm_funcs removed special smu handling of above functions and called through Powerplay API Signed-off-by:
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Darren Powell authored
v2: updated the structure name to swsmu_pm_funcs Modified Functions smu_get_performance_level() - modifed arg0 to match Powerplay API get_performance_level Other Changes added a new structure swsmu_dpm_funcs to hold smu functions for Powerplay API removed special smu handling from amdgpu_get_power_dpm_force_performance_level Signed-off-by:
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Changfeng authored
The value of max_me in amdgpu_gfx_rlc_setup_cp_table should reduce to 4 when mec2_fw is removed on asic renoir/arcturus. Or it will cause kernel NULL pointer when modprobe driver. Signed-off-by:
Changfeng <Changfeng.Zhu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Asher.Song authored
Navi12 0x7360/C7 SKU has no video support, so remove it. Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
Asher.Song <Asher.Song@amd.com> Signed-off-by:
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Dennis Li authored
To ensure user has a constant of VRAM accessible in run-time, driver reserves limit backup pages when init, and return ones when bad pages retired, to keep no change of unused memory size. v2: refine codes to calculate badpags threshold Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Signed-off-by:
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- 24 Feb, 2021 13 commits
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/amdgpu/athub_v2_1.c:79:40-45: WARNING: conversion to bool not needed here. ./drivers/gpu/drm/amd/amdgpu/athub_v2_1.c:81:40-45: WARNING: conversion to bool not needed here. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Souptick Joarder authored
>> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:9804:38: >> warning: variable 'i' is uninitialized when used here >> [-Wuninitialized] timing = &edid->detailed_timings[i]; ^ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:9714:7: note: initialize the variable 'i' to silence this warning int i; ^ = 0 1 warning generated. Initialize the variable 'i'. Reported-by:kernel test robot <lkp@intel.com> Signed-off-by:
Souptick Joarder <jrdr.linux@gmail.com> Signed-off-by:
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Sonny Jiang authored
Because of dpg, the rptr/wptr need to be saved on fw shared memory, and restore them back in RBC_RB_RPTR/WPTR in kernel at power up. Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Stylon Wang authored
This patch enables ASSR if display declares such support in DPCD. Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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John Clements authored
disable mec2 fw bin loading and reference on unsupported ASIC Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Tao Zhou authored
Remove executable configuration for the file. Reported-by:
Ming Wang <wangming01@loongson.cn> Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Acked-by:
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Prike Liang authored
In the shutdown and poweroff opt on the s0i3 system we still need un-gate the gfx clock gating and power gating before destory amdgpu device. Fixes: 628c36d7 ("drm/amdgpu: update amdgpu device suspend/resume sequence for s0i3 support") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1499Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1621:40-45: WARNING: conversion to bool not needed here. ./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1619:40-45: WARNING: conversion to bool not needed here. Reported-by:
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c:544:34-39: WARNING: conversion to bool not needed here. Reported-by:
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c:900:47-52: WARNING: conversion to bool not needed here. Reviewed-by:
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Nathan Chancellor authored
Clang warns: drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:764:2: warning: variable 'structure_size' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:770:23: note: uninitialized use occurs here memset(header, 0xFF, structure_size); ^~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:753:25: note: initialize the variable 'structure_size' to silence this warning uint16_t structure_size; ^ = 0 1 warning generated. Return in the default case, as the size of the header will not be known. Fixes: de4b7cd8 ("drm/amd/pm/swsmu: unify the init soft gpu metrics function") Link: https://github.com/ClangBuiltLinux/linux/issues/1304Reviewed-by:Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
Nathan Chancellor <nathan@kernel.org> Signed-off-by:
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Mario Kleiner authored
Spatial dithering to 10 bpc depth was disabled for all DCE's. Testing on DCE-8.3 and DCE-11.2 did not show any obvious ill effects, but a measureable precision improvement (via colorimeter) when displaying a fp16 framebuffer to a 10 bpc DP or HDMI connected HDR-10 monitor. v2: enable it for all DCEs (Alex) Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Alex Deucher <alexdeucher@gmail.com> Reviewed-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2) Signed-off-by:
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Qingqing Zhuo authored
[Why] mutex_lock() was introduced in dm_disable_vblank(), which could be called in an IRQ context. Waiting in IRQ would cause issues like kernel lockup, etc. [How] Handle code that requires mutex lock on a different thread. v2: squash in compilation fix without CONFIG_DRM_AMD_DC_DCN (Alex) v3: squash in warning fix (Wei) Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Acked-by:
Bindu Ramamurthy <bindu.r@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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- 22 Feb, 2021 9 commits
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Aric Cyr authored
[Why] No reason to have uninitialized var at top of function [How] Move it to minimum scope where it's actuallty used Signed-off-by:
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Aric Cyr authored
[Why] There is a window of time where we optimize bandwidth due to no streams enabled will enable PSTATE changing but HUBPs are not disabled yet. This results in underflow counter increasing in some hotplug scenarios. [How] Set the optimize-bandwidth flag for later processing once all the HUBPs are properly disabled. Signed-off-by:
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Vladimir Stempen authored
[why] Vendor based fan noise improvement [how] Report timing synchronizable when DP streams time frame difference is less than 0.05 percent. Adjust DP DTOs and sync displays using MASTER_UPDATE_LOCK_DB_X_Y Signed-off-by:
Vladimir Stempen <vladimir.stempen@amd.com> Acked-by:
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Yongqiang Sun authored
[Why & How] Move dmub trace buffer to uncached memory. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Eryk Brol authored
[why] This check for ASIC revision is no longer useful and causes lightup issues after a topology change in MST DSC scenario. In this case, DSC configs should be recalculated for the new topology. This check prevented that from happening on certain ASICs that do, in fact, support DSC. [how] Change the ASIC revision to instead check if DSC is supported. Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Acked-by:
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Anthony Wang authored
[Why] Some external displays with DP can use seamless boot, but their audio endpoints are only enabled after hotplug. On boot, these displays inherit UEFI timings without properly initializing audio. [How] Enable display audio when seamless booting with an external monitor over DP. Signed-off-by:
Anthony Wang <anthony1.wang@amd.com> Acked-by:
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Anthony Wang authored
[Why] Seamless boot over DP MST is not POR, but is not explicitly disabled. [How] Add check for DP MST and return false in dc_validate_seamless_boot_timing. Signed-off-by:
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