- 28 Jul, 2021 13 commits
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Eric Huang authored
This reverts commit 4e7b93ca. Revert reason: The issue has been resolved. Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Eric Huang authored
This reverts commit 7ed9876c. Revert reason: The issue has been resolved. Signed-off-by:
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Eric Huang authored
This reverts commit 024d8811. Revert reason: The issue has been resolved. Signed-off-by:
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Eric Huang authored
This reverts commit 430f8e6e. Revert reason: Issue has been resolved. Signed-off-by:
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Aric Cyr authored
This version brings along following fixed: - Guard DST_Y_PREFETCH register overflow in DCN21 - Add missing DCN21 IP parameter - Fix PSR command version - Add ETW logging for AUX failures - Add ETW log to dmub_psr_get_state - Fixed EdidUtility build errors - Fix missing reg offset for the dmcub test debug registers - Adding update authentication interface - Remove unused functions of opm state query support - Always wait for update lock status - Refactor riommu invalidation wa - Ensure dentist display clock update finished in DCN20 Reviewed-by:
Hsieh Mike <Mike.Hsieh@amd.com> Acked-by:
Solomon Chiu <solomon.chiu@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Dale Zhao authored
[Why] We don't check DENTIST_DISPCLK_CHG_DONE to ensure dentist display clockis updated to target value. In some scenarios with large display clock margin, it will deliver unfinished display clock and cause issues like display black screen. [How] Checking DENTIST_DISPCLK_CHG_DONE to ensure display clock has been update to target value before driver do other clock related actions. Reviewed-by:
Dale Zhao <dale.zhao@amd.com> Tested-by:
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Eric Yang authored
[Why] A cleaner solution, only done once on boot. [How] Remove previous workaround and configure an extra vmid one time on boot Reviewed-by:
Kazlauskas Nicholas <Nicholas.Kazlauskas@amd.com> Acked-by:
Eric Yang <Eric.Yang2@amd.com> Tested-by:
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Eric Bernstein authored
Remove code that would skip wait for lock status for Diags FPGA case Reviewed-by:
Laktyushkin Dmytro <dmytro.laktyushkin@amd.com> Acked-by:
Eric Bernstein <eric.bernstein@amd.com> Tested-by:
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Wenjing Liu authored
[why] It has been decided that opm state query support will be dropped. Therefore link encryption enabled and save current encryption states won't be used anymore and there are no foreseeable usages in the future. We will remove these two interfaces for clean up. Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Wenjing Liu authored
[why] Previously to toggle authentication, we need to remove and add the same display back with modified adjustment. This method will toggle DTM state without actual hardware changes. This is not per design and would cause potential issues in the long run. [how] We are creating a dedicated interface that does the same thing as remove and add back the display without changing DTM state. Acked-by:
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Eric Yang authored
[Why] Initializing was missing reg offsets for the dmcub test debug registers causing assert [How] Add initialization Reviewed-by:
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Mark Morra authored
[HOW] Added #ifdefs and refactored various parts of dc to allow dc_link to be built by AMD EDID UTILITY [WHY] dc_dsc was refactored moving some of the code that AMD EDID UTILITY needed to dc_link, so now dc_link needs to be included by AMD EDID UTILITY Squash in DCN config fix (Alex) Reviewed-by:
Leung Martin <Martin.Leung@amd.com> Acked-by:
Mark Morra <MarkAlbert.Morra@amd.com> Tested-by:
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- 27 Jul, 2021 7 commits
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Wyatt Wood authored
[Why] GPINT commands have the lowest priority in DMCUB, so it's possible that the command isn't processed in time. [How] Add a log to help identify this case. Reviewed-by:
Wyatt Wood <wyatt.wood@amd.com> Tested-by:
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Wyatt Wood authored
[Why] Would like to identify the cause of AUX transactions failing via ETW logs. [How] Add ETW logging for AUX failures. Reviewed-by:
Pavic Josip <Josip.Pavic@amd.com> Acked-by:
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Mikita Lipski authored
[why] For dual eDP when setting the new settings we need to set command version to DMUB_CMD_PSR_CONTROL_VERSION_1, otherwise DMUB will not read panel_inst parameter. [how] Instead of PSR_VERSION_1 pass DMUB_CMD_PSR_CONTROL_VERSION_1 Reviewed-by:
Mikita Lipski <mikita.lipski@amd.com> Tested-by:
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Victor Lu authored
[why] IP parameter min_meta_chunk_size_bytes is read for bandwidth calculations but it was never defined. [how] Define min_meta_chunk_size_bytes and initialize value to 256. Reviewed-by:
Victor Lu <victorchengchi.lu@amd.com> Tested-by:
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Pratik Vishwakarma authored
Rename amdgpu_acpi_is_s0ix_supported to better explain functionality by renaming to amdgpu_acpi_is_s0ix_active Signed-off-by:
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by:
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Victor Lu authored
[why] DST_Y_PREFETCH can overflow when DestinationLinesForPrefetch values are too large due to the former being limited to 8 bits. [how] Set the maximum value of DestinationLinesForPrefetch to be 255 * refclk period. Reviewed-by:
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Pratik Vishwakarma authored
[Why] User might change the suspend behaviour from OS. [How] Check with pm for target suspend state and set s0ix flag only for s2idle state. v2: User might change default suspend state, use target state v3: squash in build fix Suggested-by:
Lijo Lazar <Lijo.Lazar@amd.com> Signed-off-by:
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- 23 Jul, 2021 20 commits
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Hawking Zhang authored
They are initalized by hardware during power up phase, starting from sdma v5_2 generation Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Chengzhe Liu authored
In pass-through mode, after mode 1 reset, msix enablement status would lost and never receives interrupt again. So, we should restore msix status after mode 1 reset. Signed-off-by:
Chengzhe Liu <ChengZhe.Liu@amd.com> Reviewed-by:
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Roy Sun authored
The fail reason is that the vfgate is disabled Signed-off-by:
Roy Sun <Roy.Sun@amd.com> Reviewed-by:
Peng Ju Zhou <PengJu.Zhou@amd.com> Signed-off-by:
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Stylon Wang authored
[Why] Regression found in some embedded panels traces back to the earliest upstreamed ASSR patch. The changed code flow are causing problems with some panels. [How] - Change ASSR enabling code while preserving original code flow as much as possible - Simplify the code on guarding with internal display flag Bug: https://bugzilla.kernel.org/show_bug.cgi?id=213779 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1620Reviewed-by:
Stylon Wang <stylon.wang@amd.com> Signed-off-by:
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Chengzhe Liu authored
On Sienna Cichlid, in pass-through mode, if we unload the driver in BACO mode(RTPM), then the kernel would receive thousands of interrupts. That's because there is doorbell monitor interrupt on BIF, so KVM keeps injecting interrupts to the guest VM. So we should clear the doorbell interrupt status after BACO exit. v2: Modify coding style and commit message Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Luben Tuikov authored
This fixes a bug which if we probe a non-existing I2C device, and the SMU returns 0xFF, from then on we can never communicate with the SMU, because the code before this patch reads and interprets 0xFF as a terminal error, and thus we never write 0 into register 90 to clear the status (and subsequently send a new command to the SMU.) It is not an error that the SMU returns status 0xFF. This means that the SMU executed the last command successfully (execution status), but the command result is an error of some sort (execution result), depending on what the command was. When doing a status check of the SMU, before we send a new command, the only status which precludes us from sending a new command is 0--the SMU hasn't finished executing a previous command, and 0xFC--the SMU is busy. This bug was seen as the following line in the kernel log, amdgpu: Msg issuing pre-check failed(0xff) and SMU may be not in the right state! when subsequent SMU commands, not necessarily related to I2C, were sent to the SMU. This patch fixes this bug. v2: Add a comment to the description of __smu_cmn_poll_stat() to explain why we're NOT defining the SMU FW return codes as macros, but are instead hard-coding them. Such a change, can be followed up by a subsequent patch. v3: The changes are, a) Add comments to break labels in __smu_cmn_reg2errno(). b) When an unknown/unspecified/undefined result is returned back from the SMU, map that to -EREMOTEIO, to distinguish failure at the SMU FW. c) Add kernel-doc to smu_cmn_send_msg_without_waiting(), smu_cmn_wait_for_response(), smu_cmn_send_smc_msg_with_param(). d) In smu_cmn_send_smc_msg_with_param(), since we wait for completion of the command, if the result of the completion is undefined/unknown/unspecified, we print that to the kernel log. v4: a) Add macros as requested, though redundant, to be removed when SMU consolidates for all ASICs--see comment in code. b) Get out if the SMU code is unknown. v5: Rename the macro names. Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Evan Quan <evan.quan@amd.com> Cc: Lijo Lazar <Lijo.Lazar@amd.com> Fixes: fcb1fe9c ("drm/amd/powerplay: pre-check the SMU state before issuing message") Signed-off-by: -
Tao Zhou authored
Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Lang Yu authored
Asic cyan_skilfish2 won't support RLC autoload when using front door loading. We just use PSP to load firmware like gfx9 here. So add autoload_supported flag check instead of just checking firmware load type for RLC autoload. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Lang Yu authored
Enable SMU support for cyan_skilfish. v2: Squash in fix (Alex) Signed-off-by:
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Lang Yu authored
Add check_fw_version function support for cyan_skillfish. Signed-off-by:
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Lang Yu authored
Add basic ppt funcs support or cyan_skilfish. Signed-off-by:
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Lang Yu authored
Add smu11_driver_if_cyan_skillfish.h for cyan_skilfish. Signed-off-by:
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Lang Yu authored
Add smu_v11_8_ppsmc.h for cyan_skilfish. Signed-off-by:
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Lang Yu authored
Add smu_v11_8_pmfw.h for cyan_skilfish. Signed-off-by:
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Lang Yu authored
Will switch to front door loading by default after this function is stable. v2: use APU flags (Alex) Signed-off-by:
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Lang Yu authored
Add psp v11.0.8 to ip block initialization. v2: use APU flags (Alex) Signed-off-by:
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Lang Yu authored
Add psp v11.0.8 function into psp driver. Signed-off-by:
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Lang Yu authored
Introduce the psp v11.0.8 driver for cyan_skillfish. Signed-off-by:
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Lang Yu authored
The cyan_skillfish will use the mp 11.0.8. Signed-off-by:
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Tao Zhou authored
nbio version is 2.3. v2: Make it more explicit (Alex) Signed-off-by:
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