- 29 Jul, 2018 2 commits
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Alexandre Torgue authored
In case the exti line is not in line with the bank number (that is the case when there is an hole between two banks, for example GPIOK and then GPIOZ), use "st,bank-ioport" DT property to get the right exti line. Signed-off-by:
Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by:
Alexandre Torgue <alexandre.torgue@st.com> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Jisheng Zhang authored
Add the pin-controller driver for Synaptics AS370 SoC, with definition of its groups and functions. This uses the core Berlin pinctrl driver. Signed-off-by:
Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by:
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- 25 Jul, 2018 1 commit
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Linus Walleij authored
Merge tag 'samsung-pinctrl-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v4.19 1. Add handling of external wakeup interrupts mask inside the pin controller driver. Existing solution is spread between the driver and machine code. The machine code writes the mask but its value is taken from pin controller driver. This moves everything into pin controller driver allowing later to remove the cross-subsystem interaction. Also this is a necessary step for implementing later Suspend to RAM on ARMv8 Exynos5433. 2. Bring necessary suspend/resume callbacks for Exynos542x and Exynos5260. 3. Document hidden requirement about one external wakeup interrupts device node. 4. Minor documentation cleanups.
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- 24 Jul, 2018 7 commits
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Krzysztof Kozlowski authored
Replace GPL license statement with SPDX license identifier (GPL-2.0). Signed-off-by:Krzysztof Kozlowski <krzk@kernel.org>
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Krzysztof Kozlowski authored
The pinctrl driver defines an IRQ chip which handles external wakeup interrupts, therefore from logical point of view, it is the owner of external interrupt mask. The register controlling the mask belongs to Power Management Unit address space so it has to be accessed with PMU syscon regmap handle. This mask should be written to hardware during system suspend. Till now ARMv7 machine code was responsible for this which created a dependency between pin controller driver and arch/arm/mach code. Try to rework this dependency so the pinctrl driver will write external wakeup interrupt mask during late suspend. Impact on ARMv7 designs (S5Pv210 and Exynos) ============================================ This duplicates setting mask with existing machine code arch/arm/mach-exynos/suspend.c and arch/arm/mach-s5pv210/pm.c but it is not a problem - the wakeup mask register will be written twice. The machine code will be cleaned up later. The difference between implementation here and ARMv7 machine code (arch/arm/mach-*) is the time of writing the mask: 1. The machine code is writing the mask quite late during system suspend path, after offlining secondary CPUs and just before doing actual suspend. 2. The implementation in pinctrl driver uses late suspend ops, therefore it will write the mask much earlier. Hopefully late enough, after all drivers will enable or disable their interrupt wakeups (enable_irq_wake() etc). Impact on ARMv8 designs (Exynos5433 and Exynos7) ================================================ The Suspend to RAM was not supported and external wakeup interrupt mask was not written to HW. This change brings us one step closer to supporting Suspend to RAM. Signed-off-by:
Tomasz Figa <tomasz.figa@gmail.com> Tested-by:
Marek Szyprowski <m.szyprowski@samsung.com>
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Krzysztof Kozlowski authored
S5Pv210 and Exynos5433/Exynos7 have different address of EINT_WAKEUP_MASK register. Rename existing S5P_EINT_WAKEUP_MASK to avoid confusion and add new ones. Signed-off-by:
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Krzysztof Kozlowski authored
The S5Pv210 external wakeup interrupts differ from Exynos therefore separate compatible is needed. Duplicate existing flavor specific data from exynos4210_wkup_irq_chip and add new compatible for S5Pv210. At this point this new compatible does not bring anything new and works exactly as existing "samsung,exynos4210-wakeup-eint". Signed-off-by:
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Krzysztof Kozlowski authored
ARMv7 hardware (S5Pv210 and Exynos SoCs) provides only 32 external interrupts which can wakeup device from deep sleep modes. On S5Pv210 these are gph0-gph3. On all ARMv7 Exynos designs these are gpx0-gpx3. There is only one 32-bit register for controlling the external wakeup interrupt mask (masking and unmasking waking capability of these interrupts). This lead to implementation in pinctrl driver and machine code which was using static memory for storing the mask value and not caring about multiple devices of pin controller... because only one pin controller device will be handling this. Since each pin controller node in Device Tree maps onto one device, this corresponds to hidden assumption in parsing the Device Tree: external wakeup interrupts can be defined only once. Make this assumption an explicit requirement. ARMv8 Exynos5433 and Exynos7 bring additional 32 external wakeup interrupts (up to 64 total, banks gpa0-gpa3 and gpf1-gpf5) and another 32-bit wide register for controlling them. Existing code does not support it but anyway these additional interrupts will be belonging to the same pin controller device/node. Signed-off-by:
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Krzysztof Kozlowski authored
Add missing documentation for suspend and resume members of struct samsung_pin_ctrl and samsung_pinctrl_drv_data. Signed-off-by:
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Krzysztof Kozlowski authored
Suspend and resume callbacks in Exynos/S5Pv210 pin controller drivers, save and restore state of registers. This operations should be done for all banks which have external interrupts (as denoted by using EXYNOS_PIN_BANK_EINTG/EINTW macros). Add all banks of Exynos5260 and Exynos5420. This is necessary step for supporting suspend to RAM on these SoCs. Signed-off-by:
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- 17 Jul, 2018 7 commits
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Sean Wang authored
After the commit acf137951367 ("pinctrl: core: Return selector to the pinctrl driver") and the commit 47f1242d19c3 ("pinctrl: pinmux: Return selector to the pinctrl driver"), it's necessary to add the fixes needed for the pin controller drivers to use the appropriate returned selector for a negative error number returned in case of the fail at these functions. Otherwise, the driver would have a failed probe and that causes boot message cannot correctly output and devices fail to acquire their own pins. Cc: Kevin Hilman <khilman@baylibre.com> Fixes: acf137951367 ("pinctrl: core: Return selector to the pinctrl driver") Fixes: 47f1242d19c3 ("pinctrl: pinmux: Return selector to the pinctrl driver") Signed-off-by:Sean Wang <sean.wang@mediatek.com> Signed-off-by:
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Wei Yongjun authored
Add the missing unlock before return from function in the error handling case. Fixes: 0f5972033509 ("pinctrl: single: Fix group and function selector use") Signed-off-by:Wei Yongjun <weiyongjun1@huawei.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Tony Lindgren authored
With no users left for these functions let's remove them. Reported-by:
H. Nikolaus Schaller <hns@goldelico.com> Cc: Christ van Willegen <cvwillegen@gmail.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Jacopo Mondi <jacopo+renesas@jmondi.org> Cc: Paul Cercueil <paul@crapouillou.net> Cc: Sean Wang <sean.wang@mediatek.com> Signed-off-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
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Tony Lindgren authored
We must use a mutex around the generic_add functions and save the function and group selector in case we need to remove them. Otherwise the selector use will be racy for deferred probe at least. Fixes: 5a49b644 ("pinctrl: Renesas RZ/A1 pin and gpio controller") Reported-by:
Jacopo Mondi <jacopo@jmondi.org> Signed-off-by:
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Tony Lindgren authored
We must use a mutex around the generic_add functions and save the function and group selector in case we need to remove them. Otherwise the selector use will be racy for deferred probe at least. Note that struct device_node *np is unused in pcs_add_function() we remove that too and fix a checkpatch warning for bare unsigned while at it. Fixes: 571aec4d ("pinctrl: single: Use generic pinmux helpers for managing functions") Reported-by:
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Tony Lindgren authored
We must return the selector from pinmux_generic_add_function() so pin controller device drivers can remove the right group if needed for deferred probe for example. And we now must make sure that a proper name is passed so we can use it to check if the entry already exists. Note that fixes are also needed for the pin controller drivers to use the selector value. Fixes: a76edc89 ("pinctrl: core: Add generic pinctrl functions for managing groups") Reported-by:
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Tony Lindgren authored
We must return the selector from pinctrl_generic_add_group() so pin controller device drivers can remove the right group if needed for deferred probe for example. And we now must make sure that a proper name is passed so we can use it to check if the entry already exists. Note that fixes are also needed for the pin controller drivers to use the selector value. Fixes: c7059c5a ("pinctrl: core: Add generic pinctrl functions for managing groups") Reported-by:
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- 16 Jul, 2018 13 commits
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Jisheng Zhang authored
Add as370 to existing berlin pinctrl device tree binding. Signed-off-by:
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Wei Yongjun authored
Remove unneeded error handling on the result of a call to platform_get_resource() when the value is passed to devm_ioremap_resource(). Signed-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by:
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Alexandre Belloni authored
the TWI function on GPIO4 is actually a multiplexed SCL, not an original TWI SDA or SCL. Fix it. Signed-off-by:
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Lucas Stach authored
The i.MX8MQ pincontrol works in a similar way to the earlier i.MX SoCs. This driver builds on top of the imx specific pinconf handling. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
Abel Vesa <abel.vesa@nxp.com> Acked-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
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Abel Vesa authored
This adds the binding for the i.MX8MQ pin controller, in the same fashion as earlier i.MX SoCs. Signed-off-by:
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Gustavo A. R. Silva authored
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Addresses-Coverity-ID: 1292308 ("Missing break in switch") Addresses-Coverity-ID: 1292309 ("Missing break in switch") Signed-off-by:Gustavo A. R. Silva <gustavo@embeddedor.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Ludovic Desroches authored
Add support for the drive strength configuration. Usually, this value is expressed in mA. Since the numeric value depends on VDDIOP voltage, a value we can't retrieve at runtime, the controller uses low, medium and high to define the drive strength. The PIO controller accepts two values for the low drive configuration: 0 and 1. Most of the time, we don't care about the drive strength. So we keep the default value which is 0. The drive strength is advertised through the sysfs only when it has been explicitly set in the device tree i.e. if its value is different from 0. Signed-off-by:
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Gustavo A. R. Silva authored
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Warning level 2 was used: -Wimplicit-fallthrough=2 Addresses-Coverity-ID: 1463284 ("Missing break in switch") Signed-off-by: -
Jerome Brunet authored
Add the pinctrl configuration for gen_clk on gxbb and axg. gen_clk allows to output and devide several internal clocks of SoC, including most of the plls. Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
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Takeshi Kihara authored
This patch adds USB30_{PWEN,OVC} and USB3HS0_ID pins, groups and functions to the R8A77990 SoC. Signed-off-by:Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Takeshi Kihara authored
This patch adds USB0_{PWEN,OVC}_{A,B} and USB0_ID pins, groups and functions to the R8A77990 SoC. Signed-off-by: -
Yoshihiro Shimoda authored
Since the datasheet Rev.1.00 has an error about the USB ID pin name, this patch revises it. Signed-off-by:
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Takeshi Kihara authored
This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to the R8A77965 SoC. Signed-off-by:
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- 09 Jul, 2018 3 commits
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Douglas Anderson authored
If you do this on an sdm845 board: grep "" /sys/kernel/debug/pinctrl/*spmi:pmic*/pinconf-groups ...it looks like nonsense. For every pin you see listed: input bias disabled, input bias high impedance, input bias pull down, input bias pull up, ... That's because pmic_gpio_config_get() isn't complying with the rules that pinconf_generic_dump_one() expects. Specifically for boolean parameters (anything with a "struct pin_config_item" where has_arg is false) the function expects that the function should return its value not through the "config" parameter but should return "0" if the value is set and "-EINVAL" if the value isn't set. Let's fix this. From a quick sample of other pinctrl drivers, it appears to be tradition to also return 1 through the config parameter for these boolean parameters when they exist. I'm not one to knock tradition, so I'll follow tradition and return 1 in these cases. While I'm at it, I'll also continue searching for four leaf clovers, kocking on wood three times, and trying not to break mirrors. NOTE: This also fixes an apparent typo for reading PIN_CONFIG_BIAS_DISABLE where the old driver was accidentally using "=" instead of "==" and thus was setting some internal state when you tried to query PIN_CONFIG_BIAS_DISABLE. Oops. Fixes: eadff302 ("pinctrl: Qualcomm SPMI PMIC GPIO pin controller driver") Signed-off-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
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Douglas Anderson authored
If you do this on an sdm845 board: cat /sys/kernel/debug/pinctrl/3400000.pinctrl/pinconf-groups ...it looks like nonsense. For every pin you see listed: input bias bus hold, input bias disabled, input bias pull down, input bias pull up That's because msm_config_group_get() isn't complying with the rules that pinconf_generic_dump_one() expects. Specifically for boolean parameters (anything with a "struct pin_config_item" where has_arg is false) the function expects that the function should return its value not through the "config" parameter but should return "0" if the value is set and "-EINVAL" if the value isn't set. Let's fix this. From a quick sample of other pinctrl drivers, it appears to be tradition to also return 1 through the config parameter for these boolean parameters when they exist. I'm not one to knock tradition, so I'll follow tradition and return 1 in these cases. While I'm at it, I'll also continue searching for four leaf clovers, kocking on wood three times, and trying not to break mirrors. Fixes: f365be09 ("pinctrl: Add Qualcomm TLMM driver") Signed-off-by:
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Douglas Anderson authored
The pinconf_generic_dump_one() function makes the assumption that pin_config_group_get() should return -EINVAL and -ENOTSUPP just like pin_config_get() does. Document that so it's more obvious. Signed-off-by:
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- 02 Jul, 2018 2 commits
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Colin Ian King authored
The check to see if platform_get_irq failed is performed on the unsigned value of pctrl->irq[i] and the check is never true because an unsigned cannot be less than zero. Fix this by assinging the signed int ret to the return of platform_get_irq and checking ret instead. Detected by CoverityScan, CID#1470247 ("Unsigned comparison against 0") Fixes: 6c5d0736 ("pinctrl: actions: Add interrupt support for OWL S900 SoC") Signed-off-by:Colin Ian King <colin.king@canonical.com> Acked-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Andy Shevchenko authored
Reduce size of duplicated comments by switching to use SPDX identifier. No functional change. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
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- 29 Jun, 2018 4 commits
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Andy Shevchenko authored
This adds pinctrl/GPIO support for Intel Ice Lake PCH. The Ice Lake PCH GPIO is based on the same version of the Intel GPIO hardware than Intel Cannon Lake with different set of pins and ACPI ID. Signed-off-by:
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Miquel Raynal authored
Add suspend/resume hooks in pinctrl driver to handle S2RAM operations. Beyond the traditional register save/restore operations, these hooks also keep the GPIOs used for both-edge IRQ synchronized between their level (low/high) and expected IRQ polarity (falling/rising edge). Since pinctrl is an infrastructure module, its resume should be issued prior to other IO drivers. The pinctrl PM operations are requested at early/late stages for this reason. Suggested-by:
Ken Ma <make@marvell.com> Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by:
Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by:
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Manivannan Sadhasivam authored
Add interrupt support for Actions Semi OWL S900 SoC. Signed-off-by:
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Manivannan Sadhasivam authored
Add gpio interrupt bindings for Actions Semi S900 SoC. Signed-off-by:
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- 28 Jun, 2018 1 commit
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Christian Lamparter authored
This patch adds the gpio-ranges and gpio-reserved-ranges property definitions to the binding text files supported by the pinctrl-msm driver framework. gpio-ranges: For DT-based platforms the pinctrl-msm framework currently relies on the deprecated-for-DT gpiochip_add_pin_range() function to add the range of GPIOs to be handled by the pin controller. Due to interactions within gpiolib code, this causes the pinctrl-msm driver to bail out (-517) during boot when a gpio-hog is declared. This can be fatal and cause the system to not boot or reset (for a detailed explanation and call-trace, refer to patch: "pinctrl: msm: fix gpio-hog related boot issues" in this series). gpio-reserved-ranges: The binding has been added as a precaution since the TrustZone firmware (aka QSEE), which is running as the hypervisor, might have reserved certain, but undisclosed pins. Hence reading or writing to the registers for those pins will cause an XPU violation and this subsequently crashes the kernel. Signed-off-by:
Christian Lamparter <chunkeey@gmail.com> Reviewed-by:
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