- 27 Apr, 2021 3 commits
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Stephen Boyd authored
- Proper clk driver for Mediatek MT7621 SoCs * clk-ralink: MAINTAINERS: add MT7621 CLOCK maintainer staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk' staging: mt7621-dts: make use of new 'mt7621-clk' clk: ralink: add clock driver for mt7621 SoC dt: bindings: add mt7621-sysc device tree binding documentation dt-bindings: clock: add dt binding header for mt7621 clocks
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Stephen Boyd authored
Merge branches 'clk-imx', 'clk-samsung', 'clk-zynq', 'clk-rockchip' and 'clk-uniphier' into clk-next - Simplify Zynq Kconfig dependencies * clk-imx: clk: imx: Reference preceded by free clk: imx8mq: Correct the pcie1 sels clk: imx8mp: Remove the none exist pcie clocks clk: imx: Fix reparenting of UARTs not associated with stdout * clk-samsung: clk: samsung: Remove redundant dev_err calls clk: exynos7: Mark aclk_fsys1_200 as critical * clk-zynq: clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback clk: zynqmp: Drop dependency on ARCH_ZYNQMP clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected * clk-rockchip: clk: rockchip: drop MODULE_ALIAS from rk3399 clock controller clk: rockchip: drop parenthesis from ARM || COMPILE_TEST depends clk: rockchip: add clock controller for rk3568 clk: rockchip: support more core div setting dt-binding: clock: Document rockchip, rk3568-cru bindings clk: rockchip: add dt-binding header for rk3568 * clk-uniphier: clk: uniphier: Fix potential infinite loop
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Stephen Boyd authored
Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner' and 'clk-qcom' into clk-next - Use clk_hw pointers in socfpga driver - Cleanup parent data in qcom clk drivers * clk-cleanup: clk: Drop double "if" in clk_core_determine_round_nolock() comment clk: at91: Trivial typo fixes in the file sama7g5.c clk: use clk_core_enable_lock() a bit more * clk-renesas: clk: renesas: Zero init clk_init_data clk: renesas: Couple of spelling fixes clk: renesas: r8a779a0: Add CMT clocks clk: renesas: r8a7795: Add TMU clocks clk: renesas: r8a779a0: Add TSC clock clk: renesas: r8a779a0: Add TMU clocks clk: renesas: r8a77965: Add DAB clock clk: renesas: r8a77990: Add DAB clock * clk-socfpga: clk: socfpga: remove redundant initialization of variable div clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return clk: socfpga: Fix code formatting clk: socfpga: Convert to s10/agilex/n5x to use clk_hw clk: socfpga: arria10: convert to use clk_hw clk: socfpga: use clk_hw_register for a5/c5 * clk-allwinner: clk: sunxi: Demote non-conformant kernel-doc headers clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pll * clk-qcom: (45 commits) clk: qcom: rpmh: add support for SDX55 rpmh IPA clock clk: qcom: gcc-sdm845: get rid of the test clock clk: qcom: convert SDM845 Global Clock Controller to parent_data dt-bindings: clock: separate SDM845 GCC clock bindings clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLE clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE clk: qcom: a7-pll: Add missing MODULE_DEVICE_TABLE clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sm8250: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sm8150: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sc8180x: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sc7180: use ARRAY_SIZE instead of specifying num_parents clk: qcom: videocc-sm8250: use parent_hws where possible clk: qcom: videocc-sm8150: use parent_hws where possible clk: qcom: gpucc-sm8250: use parent_hws where possible clk: qcom: gpucc-sm8150: use parent_hws where possible clk: qcom: gcc-sm8350: use parent_hws where possible clk: qcom: gcc-sm8250: use parent_hws where possible clk: qcom: gcc-sm8150: use parent_hws where possible clk: qcom: gcc-sdx55: use parent_hws where possible ...
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- 13 Apr, 2021 6 commits
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Sergio Paracuellos authored
Adding myself as maintainer for mt7621 clock driver. Signed-off-by:
Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210410055059.13518-5-sergio.paracuellos@gmail.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Sergio Paracuellos authored
Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml' contains 'mediatek' as a valid vendor string. Some nodes in the device tree are using an invalid vendor string vfor 'mtk' instead. Fix all of them in dts file. Update also ralink mt7621 related code to properly match new strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc'. Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by:
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Sergio Paracuellos authored
Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by:
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Sergio Paracuellos authored
The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or some ip cores. Looking into driver code, and some openWRT patched there are another frequencies which are used in some drivers (uart, sd...). According to all of this information the clock plan for this SoC is set as follows: - Main top clock "xtal" from where all the rest of the world is derived. - CPU clock "cpu" derived from "xtal" frequencies and a bunch of register reads and predividers. - BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz. - Fixed clocks from "xtal": * "50m": 50 MHz. * "125m": 125 MHz. * "150m": 150 MHz. * "250m": 250 MHz. * "270m": 270 MHz. We also have a buch of gate clocks with their parents: * "hsdma": "150m" * "fe": "250m" * "sp_divtx": "270m" * "timer": "50m" * "pcm": "270m" * "pio": "50m" * "gdma": "bus" * "nand": "125m" * "i2c": "50m" * "i2s": "270m" * "spi": "bus" * "uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m" * "shxc": "50m" With this information the clk driver will provide clock and gates functionality from a a set of hardcoded clocks allowing to define a nice device tree without fixed clocks. Signed-off-by: -
Colin Ian King authored
The for-loop iterates with a u8 loop counter i and compares this with the loop upper limit of num_parents that is an int type. There is a potential infinite loop if num_parents is larger than the u8 loop counter. Fix this by making the loop counter the same type as num_parents. Also make num_parents an unsigned int to match the return type of the call to clk_hw_get_num_parents. Addresses-Coverity: ("Infinite loop") Fixes: 734d82f4 ("clk: uniphier: add core support code for UniPhier clock driver") Signed-off-by:Colin Ian King <colin.king@canonical.com> Reviewed-by:
Masahiro Yamada <masahiroy@kernel.org> Link: https://lore.kernel.org/r/20210409090104.629722-1-colin.king@canonical.comSigned-off-by:
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Alex Elder authored
The IPA core clock is required for SDX55. Define it. Signed-off-by:
Alex Elder <elder@linaro.org> Link: https://lore.kernel.org/r/20210409134407.841137-1-elder@linaro.orgReviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by:
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- 12 Apr, 2021 1 commit
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Stephen Boyd authored
Merge tag 'v5.13-rockchip-clocks' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: - Support for the clock controller on the new rk3568 - Some cleanups for rk3399 modularization * tag 'v5.13-rockchip-clocks' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: drop MODULE_ALIAS from rk3399 clock controller clk: rockchip: drop parenthesis from ARM || COMPILE_TEST depends clk: rockchip: add clock controller for rk3568 clk: rockchip: support more core div setting dt-binding: clock: Document rockchip, rk3568-cru bindings clk: rockchip: add dt-binding header for rk3568
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- 09 Apr, 2021 10 commits
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Stephen Boyd authored
Merge tag 'clk-v5.13-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung Pull Samsung clk driver updates from Sylwester Nawrocki: - clean up of redundant dev_err() calls after dev_ioremap_resource() - fix for the clk-exynos7 driver (part of upcoming Galaxy S6 device support) * tag 'clk-v5.13-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: Remove redundant dev_err calls clk: exynos7: Mark aclk_fsys1_200 as critical
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Dmitry Baryshkov authored
The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210409183004.1617777-4-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Signed-off-by:
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Dmitry Baryshkov authored
Separate qcom,gcc-sdm845 clock bindings from the clock-less qcom,gcc.yaml, so that we can add required clocks and clock-names properties. Signed-off-by:
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Chen Hui authored
CONFIG_IPQ_APSS_PLL is tristate option and therefore this driver can be compiled as a module. This patch adds missing MODULE_DEVICE_TABLE definition which generates correct modalias for automatic loading of this driver when it is built as an external module. Fixes: ecd2bacf ("clk: qcom: Add ipq apss pll driver") Signed-off-by:
Chen Hui <clare.chenhui@huawei.com> Reviewed-by:
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Chen Hui authored
CONFIG_QCOM_A53PLL is tristate option and therefore this driver can be compiled as a module. This patch adds missing MODULE_DEVICE_TABLE definition which generates correct modalias for automatic loading of this driver when it is built as an external module. Fixes: 0c6ab1b8 ("clk: qcom: Add A53 PLL support") Signed-off-by:
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Chen Hui authored
CONFIG_QCOM_A7PLL is tristate option and therefore this driver can be compiled as a module. This patch adds missing MODULE_DEVICE_TABLE definition which generates correct modalias for automatic loading of this driver when it is built as an external module. Fixes: 5a5223ff ("clk: qcom: Add A7 PLL support") Signed-off-by:
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Sergio Paracuellos authored
Adds device tree binding documentation for clocks in the MT7621 SOC. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Sergio Paracuellos authored
Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by:
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Stephen Boyd authored
Merge tag 'clk-imx-5.13' of https://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx Pull i.MX clk driver updates from Abel Vesa: - Fix reparenting of UART clocks by initializing only the ones associated to stdout - Correct the PCIE clocks for i.MX8MP and i.MX8MQ - Make LPCG and SCU clocks return on registering failure * tag 'clk-imx-5.13' of https://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx: Reference preceded by free clk: imx8mq: Correct the pcie1 sels clk: imx8mp: Remove the none exist pcie clocks clk: imx: Fix reparenting of UARTs not associated with stdout
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- 08 Apr, 2021 20 commits
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Chen Hui authored
There is error message within devm_ioremap_resource already, so remove the dev_err calls to avoid redundant error messages. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com>
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Quanyang Wang authored
If there is a IOCTL_SET_PLL_FRAC_MODE request sent to ATF ever, we shouldn't skip invoking PM_CLOCK_ENABLE fn even though this pll has been enabled. In ATF implementation, it will only assign the mode to the variable (struct pm_pll *)pll->mode when handling IOCTL_SET_PLL_FRAC_MODE call. Invoking PM_CLOCK_ENABLE can force ATF send request to PWU to set the pll mode to PLL's register. There is a scenario that happens in enabling VPLL_INT(clk_id:96): 1) VPLL_INT has been enabled during booting. 2) A driver calls clk_set_rate and according to the rate, the VPLL_INT should be set to FRAC mode. Then zynqmp_pll_set_mode is called to pass IOCTL_SET_PLL_FRAC_MODE to ATF. Note that at this point ATF just stores the mode to a variable. 3) This driver calls clk_prepare_enable and zynqmp_pll_enable is called to try to enable VPLL_INT pll. Because of 1), the function zynqmp_pll_enable just returns without doing anything after checking that this pll has been enabled. In the scenario above, the pll mode of VPLL_INT will never be set successfully. So adding set_pll_mode to check condition to fix it. Fixes: 3fde0e16 ("drivers: clk: Add ZynqMP clock driver") Signed-off-by:
Quanyang Wang <quanyang.wang@windriver.com> Tested-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210406153131.601701-1-quanyang.wang@windriver.comSigned-off-by:
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Quanyang Wang authored
The round_rate callback should only perform rate calculation and not involve calling zynqmp_pll_set_mode to change the pll mode. So let's move zynqmp_pll_set_mode out of round_rate and to set_rate callback. Fixes: 3fde0e16 ("drivers: clk: Add ZynqMP clock driver") Reported-by:
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Punit Agrawal authored
The clock driver depends on ZYNQMP_FIRMWARE which in turn depends on ARCH_ZYNQMP. Simplify the Kconfig by dropping the redundant dependency on ARCH_ZYNQMP as it'll be applied transitively via ZYNQMP_FIRMWARE. Signed-off-by:
Punit Agrawal <punit1.agrawal@toshiba.co.jp> Link: https://lore.kernel.org/r/20210322061754.1065367-3-punit1.agrawal@toshiba.co.jpReviewed-by:
Michal Simek <michal.simek@xilinx.com> Signed-off-by:
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Punit Agrawal authored
When booting the kernel on zynqmp based platforms such as Ultra96v2, peripheral drivers such as that for the sdcard depend on the presence of clocks. Enable the clock driver if it's dependencies are compiled to avoid building an unbootable kernel. Signed-off-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by:
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