- 16 Apr, 2010 40 commits
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Samuel Ortiz authored
Signed-off-by:
Samuel Ortiz <sameo@linux.intel.com> Signed-off-by:
Zhu Yi <yi.zhu@intel.com> Signed-off-by:
John W. Linville <linville@tuxdriver.com>
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Benoit Papillault authored
According to tests, both TSF lower and upper registers kept counting, so the higher part could have been updated after the lower part has been read, as shown in the following log where the upper part is read first and the lower part next. tsf = {00000003-fffffffd} tsf = {00000003-00000001} tsf = {00000004-0000000b} This patch corrects this by checking that the upper part has not been changed while the lower part was read. It has been tested in an IBSS network where artifical IBSS merges have been done in order to trigger hundreds of rollover for the TSF lower part. It follows the logic mentionned by Derek, with only 2 register reads needed at each additional steps instead of 3 (the minimum number of register reads is still 3). Signed-off-by:Benoit Papillault <benoit.papillault@free.fr> Signed-off-by:
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Luis R. Rodriguez authored
The first AR9003 hardware family device supported is the AR9300, which has the vendor:device id 168c:0030 Signed-off-by:
Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by:
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Vasanthakumar Thiagarajan authored
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Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by:
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Vasanthakumar Thiagarajan authored
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Luis R. Rodriguez authored
LDPC is enabled by the rate control if the its determined that the target peer supports LDPC. We would have already intersected the HT capabilities so if our peer supports LDPC so do we. Signed-off-by:
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Luis R. Rodriguez authored
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Luis R. Rodriguez authored
LDPC will be enabled through the rate control algorithm for each buffer the the tx_info flags. Signed-off-by:
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Vasanthakumar Thiagarajan authored
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Felix Fietkau <nbd@openwrt.org> Signed-off-by:
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Vasanthakumar Thiagarajan authored
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Vasanthakumar Thiagarajan authored
Also add a function to clean up tx status ring. Signed-off-by:
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Vasanthakumar Thiagarajan authored
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Luis R. Rodriguez authored
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Luis R. Rodriguez authored
Enable CRC check on the descriptor fetched from host on AR9003 upon reseting the TX queue. Signed-off-by:
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Luis R. Rodriguez authored
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Vasanthakumar Thiagarajan authored
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Luis R. Rodriguez authored
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Vasanthakumar Thiagarajan authored
Also reset tx status ring suring chip reset. Signed-off-by:
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Vasanthakumar Thiagarajan authored
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Vasanthakumar Thiagarajan authored
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Luis R. Rodriguez authored
The AR9002 hardware code enables aggregation for WEP but mac80211 doesn't enable aggregation with WEP, and the AR9003 code family does not need this so skip it for now for AR9003 but leave the code and annotate we should eventually consider how to remove this in consideration for the HAL unification goals. Signed-off-by:
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Luis R. Rodriguez authored
The asynch fifo code is specific to >= AR9287 so stuff it into the AR9002 hardware family code and skip it for AR9003 cards. Signed-off-by:
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Felix Fietkau authored
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Luis R. Rodriguez authored
This is done depending on what the EEPROM settings indicates. Signed-off-by:
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Luis R. Rodriguez authored
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Vasanthakumar Thiagarajan authored
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Luis R. Rodriguez authored
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Felix Fietkau authored
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Vasanthakumar Thiagarajan authored
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Luis R. Rodriguez authored
We add this now as OFDM spur mitigation required accessing the EEPROM for the AR9003 devices. Signed-off-by:
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Senthil Balasubramanian authored
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Senthil Balasubramanian <senthilkumar@atheros.com> Signed-off-by:
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Luis R. Rodriguez authored
Once upon a time the AR_EEPROM_MAC macro was added to let us add a random attribute to the three 4-bytes of MAC addresses entries we read from the EEPROM. This was good while a random high-enough value was used which did not conflict with any of the already existing enum eeprom_param values. With AR9003 support the enums overlap and it means we either increment the random offset or just restore the reading logic to match what the HAL has. I choose to do the later to synchronize the logic on both code bases. This should fix reading the MAC address from the EEPROM on AR9003 hardware. Signed-off-by:
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Luis R. Rodriguez authored
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Luis R. Rodriguez authored
This goes with some new shiny TX IQ calibration that AR9003 hardware family supports. Signed-off-by:
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Luis R. Rodriguez authored
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Luis R. Rodriguez authored
This is the last call on calib.c which acceses PHY stuff, with this change we calib.c is now generic between both all supported hardware families. Signed-off-by:
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Luis R. Rodriguez authored
This is so we can share routines which access this register on calib.c Signed-off-by:
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Vasanthakumar Thiagarajan authored
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Vasanthakumar Thiagarajan authored
Also move interrupt related code to mac.c Signed-off-by:
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Luis R. Rodriguez authored
The AR9003 TX/RX gain is currently initialized with the other components, so for now AR9003 does not implment this callback, after hardware bring up we can test moving the TX/RX gain there as well and if it works well move them to its own callback as well. Since all INI stuff is now moved out hw.c no longer needs to include and touch any original INI headers/structs. Signed-off-by:
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