- 02 Oct, 2018 7 commits
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Ayan Kumar Halder authored
AFBC buffers include additional metadata which increases the required allocation size. Implement the appropriate size validation and sanity checking for AFBC buffers. Added malidp specific function for framebuffer creation. This checks if the framebuffer has AFBC modifiers and if so, it verifies the necessary constraints on the size, alignment, offsets and pitch. Changes from v2: - Replaced DRM_ERROR() with DRM_DEBUG_KMS() in malidp_verify_afbc_framebuffer_caps() and malidp_verify_afbc_framebuffer_size() Signed-off-by:
Ayan Kumar halder <ayan.halder@arm.com> Reviewed-by:
Brian Starkey <brian.starkey@arm.com> Reviewed-by:
Liviu Dudau <liviu.dudau@arm.com> Signed-off-by:
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Liviu Dudau authored
Add support for compressed framebuffers that are described using the framebuffer's modifier field. Mali DP uses the rotation memory for the decompressor of the format, so we need to check for space when the modifiers are present. Signed-off-by:
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Jamie Fox authored
Mali-DP650 supports warming up the SMMU translations, by sending requsts to the SMMU before a buffer is read. There are two modes supported: - PARTIAL: could be enabled when the buffer is composed of 4K or 64K pages, the display hardware will send a configurable number of requests before the actual reading. - FULL: could be enabled when the buffer is composed of 1M or 2M pages, the display hardware will send requests before reading for all pages composing the buffer. This patch adds a mechanism for detecting the page size and set the MMU prefetch mode if possible. Changes since v1: - For imported buffers use the already populated drm_gem_cma_object.sgt instead of calling driver.gem_prime_get_sg_table, which works just for buffers allocated through the gem_cma API. Signed-off-by:
Jamie Fox <jamie.fox@arm.com> Signed-off-by:
Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com> Acked-by:
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Lowry Li authored
Checks the pixel blending mode and plane alpha value when do the plane_check. Mali DP supports blending the current plane with the background either based on the pixel alpha blending mode or by using the layer's alpha value, but not both at the same time. If both case, plane_check will return failed. Sets the HW when doing plane_update accordingly. If plane alpha is the 0xffff, set the pixel blending bits accordingly. If not we'd set ALPHA bit as zero and layer alpha value. Changes since v1: - Introduces to use it in the malidp driver, which depends on the plane alpha patch Changes since v2: - Refines the comments of drm/mali-dp patchset Changes since v3: - Adds hardware limitation check Changes since v4: - Updates on drm/malidp, hardware limitation check only when the format has alpha pixel. - Rebases on drm-misc-next. Signed-off-by:
Lowry Li <lowry.li@arm.com> Acked-by:
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Alexandru Gheorghe authored
Smart layer enable rectangles is set to 1 when the driver is probed, however when doing pm_suspend the value is lost and it's not set again making the SMART_LAYER unusable, fix that by initializing the number of rectangles everytime we do a plane update. Signed-off-by:
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Alexandru Gheorghe authored
When we want to writeback to memory in NV12 format we need to program the RGB2YUV coefficients. Currently, we don't program the coefficients and NV12 doesn't work at all. This patchset fixes that by programming a sane default(bt709, limited range) as rgb2yuv coefficients. In the long run, probably we need to think of a way for userspace to be able to program that, but for now I think this is better than not working at all or not advertising NV12 as a supported format for memwrite. Changes since v1: - Write the rgb2yuv coefficients only once, since we don't change them at all, just write them the first time NV12 is programmed, suggested by Brian Starkey, here [1] [1] https://lists.freedesktop.org/archives/dri-devel/2018-August/186819.htmlSigned-off-by:
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Alexandru Gheorghe authored
Currently, if userspace calls drm_wait_vblank before the crtc is activated the crtc vblank_enable hook is called, which in case of malidp driver triggers some warninngs. This happens because on device init we don't inform the drm core about the vblank state by calling drm_crtc_vblank_on/off/reset which together with drm_vblank_get have some magic that prevents calling drm_vblank_enable when crtc is off. Signed-off-by:
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- 27 Sep, 2018 33 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
More new features and fixes for 4.20: - Add dynamic powergating support for VCN on picasso - Scheduler cleanup - Vega20 support for KFD - DC cleanups and bug fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180927184348.2696-1-alexander.deucher@amd.com
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git://anongit.freedesktop.org/tegra/linuxDave Airlie authored
drm/tegra: Changes for v4.20-rc1 This contains initial Tegra194 support as well as a couple of fixes for DMA/IOMMU integration. Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
Driver Changes: - Bugzilla 107600: Fix stuttering video playback on MythTV on old hardware (Chris) - Avoid black screen when using CSC coefficient matrix (Raviraj) - Hammer PDs on Baytrail to make sure they reload (Chris) - Capture some objects if unable to capture all, on error (Chris) - Add W/A for 16 GB DIMMs on SKL+ (Mahesh) - Only enable IPC for symmetric memory configurations on KBL+ (Mahesh) - Assume pipe A to have maximum stride limits (Ville) - Always update update OA contexts via context image (Tvrtko) - Icelake enabling patches (Madhav, Dhinakaran) - Add Icelake DMC firmware (Anusha) - Fixes for CI found corner cases (Chris) - Limit the backpressure for request allocation (Chris) - Park GPU on module load so usage starts from known state (Chris) - Flush tasklet when checking for idle (Chris) - Use coherent write into the context image on BSW+ (Chris) - Fix possible integer overflow for framebuffers that get aligned past 4GiB (Ville) - Downgrade fence timeout from warn to notice and add debug hint (Chris) - Fixes to multi function encoder code (Ville) - Fix sprite plane check logic (Dan, Ville) - PAGE_SIZE vs. I915_GTT_PAGE_SIZE fixes (Ville) - Decode memory bandwidth and parameters for BXT and SKL+ (Mahesh) - Overwrite BIOS set IPC value from KMS (Mahesh) - Multiple pipe handling code cleanups/restructurings/optimizations (Ville) - Spare low 4G address for non-48bit objects (Chris) - Free context_setparam of struct_mutex (Chris) - Delay updating ring register state on resume (Chris) - Avoid unnecessarily copying overlay IOCTL parameters (Chris) - Update GuC power domain states even without submission (Michal) - Restore GuC preempt-context across S3/S4 (Chris) - Add kernel selftest for rapid context switching (Chris) - Keep runtime power management ref for live selftests (Chris) - GEM code cleanups (Matt) Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 4.20: UAPI Changes: - None Cross-subsystem Changes: - MAINTAINERS: Move udl, mxsfb, and fsl-dcu into drm-misc (Stefan, Sean) Core Changes: - syncobj: Check condition before returning timeout in schedule() (Chris) Driver Changes: - various: First wave of drm_fbdev_generic_setup() conversions (Noralf) - bochs/virtio: More format byte-order improvements (Gerd) - mxsfb: A couple fixes + add runtime pm support (Leonard) - virtio: Add vmap support for prime objects (Ezequiel) Cc: Stefan Agner <stefan@agner.ch> Cc: Sean Paul <sean@poorly.run> Cc: Noralf Trønnes <noralf@tronnes.org> Cc: Gerd Hoffman <kraxel@redhat.com> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ezequiel Garcia <ezequiel@collabora.com> Signed-off-by:
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Nayan Deshmukh authored
having a delayed work item per job is redundant as we only need one per scheduler to track the time out the currently executing job. v2: the first element of the ring mirror list is the currently executing job so we don't need a additional variable for it v3: squash in fixes for v3d and etnaviv Signed-off-by:
Nayan Deshmukh <nayan26deshmukh@gmail.com> Suggested-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com>
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Nathan Chancellor authored
Clang generates warnings when one enumerated type is implicitly converted to another. drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/ppatomfwctrl.c:532:57: warning: implicit conversion from enumeration type 'enum atom_smu11_syspll0_clock_id' to different enumeration type 'BIOS_CLKID' (aka 'enum atom_smu9_syspll0_clock_id') [-Wenum-conversion] if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_SOCCLK_ID, &frequency)) In this case, that is expected behavior. To make that clear to Clang without explicitly casting these values, change id's type to uint8_t in pp_atomfwctrl_get_clk_information_by_clkid so no conversion happens. Reported-by:Nick Desaulniers <ndesaulniers@google.com> Signed-off-by:
Nathan Chancellor <natechancellor@gmail.com> Signed-off-by:
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Shaoyun Liu authored
Firmware have the workaround to replace the atomic Ops with read-modify-write on CP side. User should not expect atomic Ops on system memory works normally if system didn't not support it. Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Jernej Skrabec authored
R40 DE2 mixers are similar to those found in A83T, except it needs different clock settings. Add a compatibles for them. Reviewed-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by:
Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-14-jernej.skrabec@siol.net
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Chen-Yu Tsai authored
This reverts commit 3510e7a7. During the 4.19 merge window for drm-misc, two patches critical to supporting the display pipeline on the Allwinner R40 SoC were missed. They were applied later but missed the merge window deadline. As a result 4.19-rc1 kernel would crash on the R40 when it couldn't parse the new device tree structure. We ended up removing support for the R40 display pipeline for 4.19. Since the missing patches are already merged for 4.20, we can now revert the commit that removed support. Signed-off-by:
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Sean Paul authored
Backmerging 4.19-rc5 to pick up sun4i fix Signed-off-by: -
Alex Deucher authored
Fix some indentation issues. Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Alex Deucher authored
expects argument of type ‘unsigned int’ has type ‘long int’ Fixes: 52e211c1 ("drm/amdgpu:Add error message when register failed to reach expected value") Reviewed-by:
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James Zhu authored
Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso Signed-off-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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James Zhu authored
Add functions to support VCN DPG pause mode. Signed-off-by:
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James Zhu authored
Add DPG pause state to support VCN DPG mode. Signed-off-by:
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James Zhu authored
Add DPG mode start/stop/mc_resume/clock_gating to support vcn 1.0 DPG mode. Signed-off-by:
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James Zhu authored
Some registers read/write needs program through SDRAM pool under DPG mode. Signed-off-by:
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James Zhu authored
Add DPG support flag for VCN DPG mode. Signed-off-by:
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James Zhu authored
New register offset/mask need to be added to support VCN DPG mode. Signed-off-by:
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James Zhu authored
Use register UVD_SCRATCH9 for VCN ring/ib test. Since those registers can't be directly accessed under DPG(Dynamic Power Gate) mode. Signed-off-by:
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Christian König authored
Everything that isn't related to the IH ring. Signed-off-by:
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Christian König authored
Add a callback to amdgpu_ih_process to remove most of the IV logic. Signed-off-by:
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Andrey Grodzovsky authored
Only print the warning if there was actually some fence processed from the SW fallback timer. v2: Add return value to amdgpu_fence_process to let amdgpu_fence_fallback know fences were actually processed and then print the warning. v3: Always return true if seq != last_seq Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Christian König authored
Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings. Signed-off-by:
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Christian König authored
We always want those to be setup correctly. Signed-off-by:
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Christian König authored
That is superflous here. Signed-off-by:
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Huang Rui authored
While the apg_end address is 0xffffffff, if add 1 with it, the value will be overflow and roll back to 0. So when 0 is written to mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, the system aperture is actually disabled. And so any access to vram will trigger a page fault. Raven2's HW issue only need increase the vram end address, and needn't do it on the agp. Signed-off-by:
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Rex Zhu authored
Need to disable dpm features before halt rlc. Acked-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
the CG related registers have been programed in golden setting PG register default value is 0. Acked-by:
Hang Zhou <hang.zhou@amd.com> Signed-off-by:
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Rex Zhu authored
before halt rlc/cp, need to 1. enter rlc safe mode 2. wait rlc/cp idle Acked-by:
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Rex Zhu authored
change function name gfx_v6/7/8/9_0_gpu_init to gfx_v6/7/8/9_0_constants_init. this function is just for init gfx constants such as max pipes, render backends... Reviewed-by:
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Andrey Grodzovsky authored
Deactivate SW interrupt fallback when all emited fences are completed. Also switch interrupt SW fallback message from INFO to WARN. v2: shorten the warning message a bit and only re-activate the timer during processing if it was already activated before. (Christian) Signed-off-by:
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Shaoyun Liu authored
Add Vega20 device IDs, device info and enable it in KFD. Signed-off-by:
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