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- 31 Mar, 2023 9 commits
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Garmin.Chang authored
Add MT8188 mfg clock controller which provides clock gate control for GPU. Signed-off-by:
Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-11-Garmin.Chang@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Garmin.Chang authored
Add MT8188 ipesys clock controller which provides clock gate control for Image Process Engine. Signed-off-by:
Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-10-Garmin.Chang@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Garmin.Chang authored
Add MT8188 imgsys clock controllers which provide clock gate control for image IP blocks. Signed-off-by:
Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-9-Garmin.Chang@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Garmin.Chang authored
Add MT8188 ccusys clock controller which provides clock gate control in Camera Computing Unit. Signed-off-by:
Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-8-Garmin.Chang@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Garmin.Chang authored
Add MT8188 camsys clock controllers which provide clock gate control for camera IP blocks. Signed-off-by:
Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-7-Garmin.Chang@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Garmin.Chang authored
Add MT8188 infrastructure clock controller which provides clock gate control for basic IP like pwm, uart, spi and so on. Signed-off-by:
Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-6-Garmin.Chang@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Garmin.Chang authored
Add MT8188 peripheral clock controller which provides clock gate control for ethernet/flashif/pcie/ssusb. Signed-off-by:
Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-5-Garmin.Chang@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Garmin.Chang authored
Add MT8188 topckgen clock controller which provides muxes, dividers to handle variety clock selection in other IP blocks. Signed-off-by:
Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-4-Garmin.Chang@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Garmin.Chang authored
Add MT8188 apmixedsys clock controller which provides Plls generated from SoC 26m and ssusb clock gate control. Signed-off-by:
Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-3-Garmin.Chang@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 13 Mar, 2023 11 commits
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AngeloGioacchino Del Regno authored
In preparation for migrating mt8135 clocks to the common simple probe mechanism, move the apmixedsys clocks to a different file. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-51-angelogioacchino.delregno@collabora.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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AngeloGioacchino Del Regno authored
This is the last man standing in clk-mt8192.c that won't allow us to use the module_platform_driver() macro, and for *no* good reason. Move it to clk-mt8192-apmixedsys.c and while at it, also add a .remove() callback for it. Also, since the need for "clk-mt8192-simple" and "clk-mt8192" was just due to them being in the same file and probing different clocks, and since now there's just one platform_driver struct per file, it seemed natural to rename the `-simple` variant to just "clk-mt8192". Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Tested-by:
Miles Chen <miles.chen@mediatek.com> Tested-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-48-angelogioacchino.delregno@collabora.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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AngeloGioacchino Del Regno authored
When building clock drivers for MT8186, some may want to build in only some of them to, for example, get CPUFreq up faster, and some may want to leave out some clock drivers entirely as a machine may not need the Warp Engine or the camera ISP (hence, their clock drivers). Split the various clock drivers in their own configuration options, keeping MT8186 configuration options consistent with other MediaTek SoCs. While at it, also allow building the remaining clock drivers as modules by switching COMMON_CLK_MT8186 to tristate. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-47-angelogioacchino.delregno@collabora.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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AngeloGioacchino Del Regno authored
MT8195 clock drivers were encapsulated in one single (and big) Kconfig option: there's no reason to do that, as it is totally unnecessary to build in all or none of them. Split them out: keep boot-critical clocks as bool and allow choosing non critical clocks as tristate. As a note, the dependencies of VDEC/VENCSYS and CAM/IMG/IPE/WPESYS are not for build-time but rather for runtime, as clocks registered by those have runtime dependencies on either or both VPP and IMGSYS. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Tested-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-40-angelogioacchino.delregno@collabora.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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AngeloGioacchino Del Regno authored
In preparation for migrating mt8516 clocks to the common simple probe mechanism, convert the apmixedsys to be a separated platform driver and move it to clk-mt8516-apmixedsys.c. While at it, also fix some indentation issues. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-29-angelogioacchino.delregno@collabora.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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AngeloGioacchino Del Regno authored
The infracfg driver cannot be converted to clk_mtk_simple_probe() as it registers cpumuxes, which is not supported on the common probing mechanism: for this reason, move it to its own file. While at it, also convert it to be a platform driver instead; to do so, also add a .remove() callback for this driver. During the conversion, error handling was added to the infracfg probe function. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-27-angelogioacchino.delregno@collabora.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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AngeloGioacchino Del Regno authored
In preparation for migrating mt7622 clocks to the common simple probe mechanism, move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-25-angelogioacchino.delregno@collabora.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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AngeloGioacchino Del Regno authored
In preparation for migrating all other mt8183 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it and fix some indentation issues in the PLLs table. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Tested-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-20-angelogioacchino.delregno@collabora.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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AngeloGioacchino Del Regno authored
In preparation for migrating all other MT8167 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, also migrate away from the legacy CLK_OF_DECLARE and convert this clock driver to be a platform_driver instead. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-17-angelogioacchino.delregno@collabora.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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AngeloGioacchino Del Regno authored
In preparation for migrating all other mt8365 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-12-angelogioacchino.delregno@collabora.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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AngeloGioacchino Del Regno authored
The only clock driver that does not support mtk_clk_simple_probe() is apmixedsys: in preparation for enabling module build of non-critical mt2712 clocks, move this to its own file. While at it, also fix some indentation issues in the PLLs table. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-9-angelogioacchino.delregno@collabora.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 31 Jan, 2023 2 commits
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Daniel Golle authored
Add MT7981 clock support, include topckgen, apmixedsys, infracfg and ethernet subsystem clocks. The drivers are based on clk-mt7981.c which can be found in MediaTek's SDK sources. To be fit for upstream inclusion the driver has been split into clock domains and the infracfg part has been significantly de-bloated by removing all the 1:1 factors (aliases). Signed-off-by:
Jianhui Zhao <zhaojh329@gmail.com> Signed-off-by:
Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.orgReviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> [sboyd@kernel.org: Add module license] Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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AngeloGioacchino Del Regno authored
Split the giant clock driver for MT8173 into smaller drivers and make it possible to build the non boot critical clock controller drivers as modules by adding remove functions and both module description and license where needed. While at it, also change a mtk_register_reset_controller() call to mtk_register_reset_controller_with_dev() in mt8173-infracfg. Some spare code style cleanups were also performed. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230120092053.182923-11-angelogioacchino.delregno@collabora.comTested-by:
Mingming Su <mingming.su@mediatek.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 29 Nov, 2022 1 commit
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Johnson Wang authored
To implement frequency hopping and spread spectrum clocking function, we introduce new clock type and APIs to handle FHCTL hardware. Co-developed-by:
Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by:
Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by:
Johnson Wang <johnson.wang@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221121122957.21611-4-johnson.wang@mediatek.comSigned-off-by:
Chen-Yu Tsai <wenst@chromium.org>
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- 30 Sep, 2022 1 commit
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Fabien Parent authored
Add clock drivers for MT8365 SoC. Signed-off-by:
Fabien Parent <fparent@baylibre.com> Signed-off-by:
Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220822152652.3499972-5-msp@baylibre.comReported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 26 Sep, 2022 1 commit
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AngeloGioacchino Del Regno authored
Add the clock drivers for the entire clock tree of MediaTek Helio X10 MT6795, including system clocks (apmixedsys, infracfg, pericfg, topckgen) and multimedia clocks (mmsys, mfg, vdecsys, vencsys). Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220921091455.41327-9-angelogioacchino.delregno@collabora.comSigned-off-by:
Chen-Yu Tsai <wenst@chromium.org>
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- 25 Apr, 2022 14 commits
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Chun-Jie Chen authored
Add MT8186 ipesys clock controller which provides clock gate control for Image Process Engine. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-16-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen authored
Add MT8186 mdpsys clock controller which provides clock gate control in Multimedia Data Path. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-15-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen authored
Add MT8186 camsys clock controllers which provide clock gate control for camera IP blocks. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-14-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen authored
Add MT8186 vencsys clock controller which provide clock gate control for video encoder. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-13-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen authored
Add MT8186 vdec clock controller which provide clock gate control for video decoder. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-12-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen authored
Add MT8186 imgsys clock controllers which provide clock gate control for image IP blocks. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-11-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen authored
Add MT8186 wpesys clock controllers which provide clock gate control in Wrapping Engine. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-10-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen authored
Add MT8186 mmsys clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start mmsys clock driver. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-9-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen authored
Add MT8186 mfg clock controller which provides clock gate control for GPU. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-8-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen authored
Add MT8186 imp i2c wrapper clock controllers which provide clock gate control in i2c IP blocks. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-7-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen authored
Add MT8186 apmixedsys clock controller which provides Plls generated from SoC. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-6-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen authored
Add MT8186 infrastructure clock controller which provides clock gate control for basic IP like pwm, uart, spi and so on. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-5-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen authored
Add MT8186 topckgen clock controller which provides muxes, dividers to handle variety clock selection in other IP blocks. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-4-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Chun-Jie Chen authored
Add MT8186 mcusys clock controller which provides muxes to select the clock source of APMCU. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-3-chun-jie.chen@mediatek.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 07 Jan, 2022 1 commit
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Sam Shih authored
Add MT7986 clock support, include topckgen, apmixedsys, infracfg, and ethernet subsystem clocks. Signed-off-by:
Sam Shih <sam.shih@mediatek.com> Link: https://lore.kernel.org/r/20211217121148.6753-4-sam.shih@mediatek.comReviewed-by:
Ryder Lee <ryder.lee@kernel.org> [sboyd@kernel.org: Fix typos in Kconfig, there are more existing typos from where they were copied from of but whatever] Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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