- 20 May, 2015 40 commits
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Tvrtko Ursulin authored
v2: Split strings to 80 char, add ddi_pll_sel and fixed typo. (Damien Lespiau) Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Ander Conselvan de Oliveira authored
In the following commit, the place where the contents of dpll_hw_state in crtc_state where zeroed was changed. Prior to that commit, it happened when the new state was allocated, but now that happens just before the call the .crtc_compute_clock() hook. The DP code for SKL, however, sets up the (private) PLL in the encoder compute config function that has already run by the time that memset() is reached, causing the previous value to be lost. This patch fixes the issue by moving the memset() down the call chain, so that it is only called if the values in dpll_hw_state are going to be updated. commit 4978cc93 Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Tue Apr 21 17:13:21 2015 +0300 drm/i915: Preserve shared DPLL information in new pipe_config Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90462Signed-off-by:
Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
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Jani Nikula authored
Add one explicit discard of __iomem address space qualifier in validate_vbt(), and respect it otherwise. This adds clarity in the code, and reduces the sparse warnings from the module to just one. Quoting Daniel, "The vbt really is plain old memory. Except that it's reserved in the e820 table as something special and hence treated as io range by the kernel. But it is memory, hence casting away the __iomem is imo the right approach." Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Tvrtko Ursulin authored
Just so it is grouped logically in line with other data and makes a rather verbose output a bit shorter. Signed-off-by:
Chandra Konduru <chandra.konduru@intel.com> Signed-off-by:
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Jani Nikula authored
Improve clarity. No functional changes. Signed-off-by:
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Jani Nikula authored
We never pass a non-NULL vbt to validate_vbt, and we can safely expect the callers to not change. Signed-off-by:
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Damien Lespiau authored
Ville noticed in another patch we we didn't need them at all, so remove them. It's worth saying that it makes no difference to code generated as gcc is clever enough to optimize it out. v2: Remove 'break' after 'return' in switches (Ville) Suggested-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Currently DSI PLL N1 is hardcoded off. Make it possible to use it later. This should have no functional changes for now. v2: s/ffz(~(n))/ffs(n) - 1/ (Ville) Signed-off-by:
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Animesh Manna authored
Added docbook info regarding context save and restore (CSR) firmware support added from gen9 onwards to drive newly added DMC (Display microcontroller) in display engine. v1: Initial version as RFC. v2: Used "DOC:" tag for csr description based on review comment from Daniel. Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Signed-off-by:
A.Sunil Kamath <sunil.kamath@intel.com> Signed-off-by:
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Mika Kuoppala authored
Reading from disconnected ports will spit out timeout error on the dmesg. Skip the attempted read if the port is not connected and avoid confusing users/testcases about expected timeouts. This new dpcd debugfs entry was introduced by commit aa7471d2 ("drm/i915: add i915 specific connector debugfs file for DPCD") v2 by Jani: move the check at the top, out of the loop. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90060 Tested-by: yex.tian@intel.com Cc: Jani Nikula <jani.nikula@intel.com> Cc: Bob Paauwe <bob.j.paauwe@intel.com> Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
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Dan Carpenter authored
There is an extra semi-colon on the if statement so the debug output always says "Failed to write EDID checksum" even when it didn't fail. Fixes: 559be30c ('drm/i915: Implement the intel_dp_autotest_edid function for DP EDID complaince tests') Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Damien Lespiau authored
Signed-off-by:
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Damien Lespiau authored
We now prefix our functions/enums/data with the first platform it has been introduced. Do that for the primary plane formats. Signed-off-by:
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Damien Lespiau authored
We advertize C8 in the primary plane formats didn't have the corresponding code to set PLANE_CTL accordingly. Signed-off-by:
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Damien Lespiau authored
Let's be consistent with the others skl_plane_ctl_*() functions and use a MISSING_CASE(). Not only that, but it's a rude to BUG() the whole machine here. Signed-off-by:
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Damien Lespiau authored
No reason to not follow the 80 chars rule, renaming the local variable makes it easy. Cc: Chandra Konduru <chandra.konduru@intel.com> Signed-off-by:
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Damien Lespiau authored
We usually use a new line before those kind of return statements. Also the various skl_plane_ctl*() functions weren't consistent. Cc: Chandra Konduru <chandra.konduru@intel.com> Signed-off-by:
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Damien Lespiau authored
Cc: Chandra Konduru <chandra.konduru@intel.com> Signed-off-by:
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Jani Nikula authored
Improve readability. No functional changes. v2: use more rational types (Ville) Signed-off-by:
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Jani Nikula authored
Do not expose invalid gmbus pins as i2c devices to userspace. Signed-off-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Jani Nikula authored
Do not expose invalid gmbus pins as i2c devices to userspace. Signed-off-by:
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Jani Nikula authored
Make input and output of validate_vbt const, and fix the fallout. We shouldn't modify the VBT, so make the compiler help us here. v2: use pointer arithmetics on void* to simplify (Ville) Signed-off-by:
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Jani Nikula authored
Make input and output of find_section const, and fix the fallout. We shouldn't modify the VBT, so make the compiler help us here. Signed-off-by:
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Ville Syrjälä authored
Use HOTPLUG_INT_STATUS_G4X instead of HOTPLUG_INT_STATUS_I915 on VLV/CHV so that we don't confuse the AUX status bits with SDVO status bits. Avoid pointless log spam as below while handling AUX interrupts: [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000 [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000 [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000 [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000 [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000 [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064 Note that there's no functional issue, it's just that the sdvo bits overlap with the dp aux bits. Hence every time we receive an aux interrupt we also think there's an sdvo hpd interrupt, but due to lack of any sdvo encoders nothing ever happens because of that. Signed-off-by:
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Ville Syrjälä authored
Remove some inline keywords. One of the functions has clearly outgrown it anyway, so let's just leave it to the compiler. Signed-off-by:
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Mika Kuoppala authored
The check for start + length >= total_vm_size is wrong since start + length can be exactly the size of the vm. Fix the check to allow allocation to boundary. Fixes a regression in commit 4dd738e9 ("drm/i915: Fix 32b overflow check in gen8_ppgtt_alloc_page_directories") Testcase: igt/gem_evict_everything/swapping-interruptible Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90399Tested-by:
Lu Hua <huax.lu@intel.com> Cc: Chris Wilson <chris@chris.wilson.co.uk> Cc: Dave Gordon <david.s.gordon@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Signed-off-by:
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Chandra Konduru authored
During check_crtc_state, scaler_id mispatch is being reported for HSW. This is applicable for skl+ and not for HSW. It is introduced by commit id: commit a1b2278e Author: Chandra Konduru <chandra.konduru@intel.com> Date: Tue Apr 7 15:28:45 2015 -0700 drm/i915: skylake panel fitting using shared scalers This patch will make sure that we leave scaler_id as 0 for platforms before skl and set for skl+ only. This way scaler_id check during check_crtc_state will pass for both prior to skl and skl+ platforms. v2: -Leave scaler_id as 0 for gen < 9 (Daniel) Signed-off-by: -
Chris Wilson authored
As we perform the mmio-flip without any locking and then try to acquire the struct_mutex prior to dereferencing the request, it is possible for userspace to queue a new pageflip before the worker can finish clearing the old state - and then it will clear the new flip request. The result is that the new flip could be completed before the GPU has finished rendering. The bugs stems from removing the seqno checking in commit 536f5b5e Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Thu Nov 6 11:03:40 2014 +0200 drm/i915: Make mmio flip wait for seqno in the work function Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by:
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Chris Wilson authored
Synchronising to an object active on the same ring is a no-op, for the benefit of execbuffer scheduler. However, for CS flips this means that we can forgo checking whether the last write request of the object is actually queued and more importantly whether the cache flush for the write was emitted. Signed-off-by:
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Chris Wilson authored
We no longer interpolate domains in the same manner, and even if we did, we should trust setting either of the other write domains would trigger an invalidation rather than force it. Remove the tweaking of the read_domains since it serves no purpose and use i915_gem_object_wait_rendering() directly. Note that this goes back to commit a8198eea Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Wed Apr 13 22:04:09 2011 +0100 drm/i915: Introduce i915_gem_object_finish_gpu() and gpu domain tracking died in commit cc889e0f Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Jun 13 20:45:19 2012 +0200 drm/i915: disable flushing_list/gpu_write_list which is more than 1 year older. Signed-off-by:
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Peter Antoine authored
If an batch ends while the IRQs are not turned on the notification can go missing and the GPU can hang. So generate a warning in this case. Signed-off-by:
Peter Antoine <peter.antoine@intel.com> Signed-off-by:
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Chandra Konduru authored
In skylake update plane functions, intel_tile_height() is called with bits_per_pixel instead of pixel_format. Correcting it. Signed-off-by:
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Tvrtko Ursulin authored
Signed-off-by:
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Deepak S authored
After feedback from the hardware team, now we set the GPU min/idel freq to RPe. Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the frequency to RPn, punit is failing to change the vgg input voltage to minimum :( Since Punit validates the rps range [RPe, RP0]. This patch removes unused cherryview_rps_min_freq function. v2: Change commit message v3: set min_freq before idle_freq (chris) v4: Squash 'Remove unused rps min function' patch Signed-off-by:
Deepak S <deepak.s@linux.intel.com> Acked-by:
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Deepak S authored
It is observed on BSW that requesting a new frequency from Punit does nothing when the GPU is in rc6, and if we let GPU enter rc6 with a high frequency, Vnn remains slightly higher than at minimum frequency. Extending vlv_set_rps_idle() workaround on CHV/BSW. v2: Update commit msg (Ville) suggested-by:
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Deepak S authored
When GPU is idle on VLV, Request freq to punit should be good enough to get the voltage back to VNN. Also, make sure gfx clock force applies before requesting the freq fot vlv. v2: Do forcewake before setting idle frequency (ville) Update function comments to match the code (Deepak) v3: Fix get/put across idle frequency Request. (Ville) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75244suggested-by:Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Damien Lespiau authored
As we're doing throughout the code, being optimistic that platform n + 1 will mostly reuse the same things as platform n allows us to minimize the enabling work needed. This time, it's about the number of WM levels. Signed-off-by:
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Maarten Lankhorst authored
With the recent modeset internal rework, we wind up setting crtc_state->enable to false, but leave crtc_state->active as true following a drmModeSetCrtc(fb=0), which is incorrect. This mismatch gets caught by drm_atomic_crtc_check() and causes subsequent atomic operations (such as plane updates while the CRTC is disabled) to fail. Bisect points to commit dad9a7d6d96630182fb52aae7c3856e9e7285e13 Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Tue Apr 21 17:13:19 2015 +0300 drm/i915: Use atomic helpers for computing changed flags as the commit that actually triggers the regression. The difference compared to (which this patch reverts) commit 90d46906 Author: Matt Roper <matthew.d.roper@intel.com> Date: Thu May 7 14:31:28 2015 -0700 drm/i915: Set crtc_state->active to false when CRTC is disabled (v2) is that we know keep state->active/enable in sync for all legacy modeset paths, as it should be. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reported-and-Tested-by:Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> [danvet: Directly squash in the revert and augment the commit message.] Signed-off-by:
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Chandra Konduru authored
Skylake nv12 format requires dbuf (aka. ddb) calculations and programming for each of y and uv sub-planes. Made minor changes to reuse current dbuf calculations and programming for uv plane. i.e., with this change, existing computation is used for either packed format or uv portion of nv12 depending on incoming format. Added new code for dbuf computation and programming for y plane. This patch is a pre-requisite for adding NV12 format support. Actual nv12 support is coming in later patches. Signed-off-by:
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Masanari Iida authored
This patch fix spelling typo in intel_runtime_pm.c Signed-off-by:
Masanari Iida <standby24x7@gmail.com> Signed-off-by:
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