- 14 Aug, 2017 3 commits
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Daniel Vetter authored
Blocking in a worker is ok, that's what the unbound_wq is for. And it unifies the paths between the blocking and nonblocking commit, giving me just one path where I have to implement the deadlock avoidance trickery in the next patch. I first tried to implement the following patch without this rework, but force-completing i915_sw_fence creates some serious challenges around properly cleaning things up. So wasn't a feasible short-term approach. Another approach would be to simple keep track of all pending atomic commit work items and manually queue them from the reset code. With the caveat that double-queue in case we race with the i915_sw_fence must be avoided. Given all that, taking the cost of a double schedule in atomic for the short-term fix is the best approach, but can be changed in the future of course. v2: Amend commit message (Chris). v3: Add comment explaining why we do nothing in the sw_fence complete callback (Michel). Reviewed-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> (v2) Cc: Michel Thierry <michel.thierry@intel.com> Reviewed-by:
Michel Thierry <michel.thierry@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170808080828.23650-2-daniel.vetter@ffwll.ch
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Daniel Vetter authored
... using the biggest hammer we have. This is essentially a weaponized version of the timeout-based wedging Chris added in commit 36703e79 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu Jun 22 11:56:25 2017 +0100 drm/i915: Break modeset deadlocks on reset Because defense-in-depth is good it's good to still have both. Also note that with the locking change we can now restrict this a lot (old gpus and special testing only), so this doesn't kill the TDR benefits on at least anything remotely modern. And futuremore with a few tricks it should be possible to make a much more educated guess about whether an atomic commit is stuck waiting on the gpu (atomic_t counting the pending i915_sw_fence used by the atomic modeset code should do it), so we can improve this. But for now just start with something that is guaranteed to recover faster, for much better CI througput. This defacto reverts TDR on these platforms, but there's not really a single commit to specify as the sole offender. v2: Add a debug message to explain what's going on. We can't DRM_ERROR because that spams CI. And the timeout based fallback still prints a DRM_ERROR, in case something goes wrong. v3: Fix comment layout (Michel) Fixes: 4680816b ("drm/i915: Wait first for submission, before waiting for request completion") Fixes: 221fe799 ("drm/i915: Perform a direct reset of the GPU from the waiter") Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> (v2) Cc: Michel Thierry <michel.thierry@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> (v2) Reviewed-by:
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Mika Kuoppala authored
Update gen9 renderstate to account the, long overdue, changes for igt commit 5c07135b7bd2 ("tools/null_state/gen9: Send all components in VF state"). Signed-off-by:Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20170810110451.31635-1-mika.kuoppala@intel.com
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- 12 Aug, 2017 3 commits
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Michal Wajdeczko authored
We should emphasize that irq raising function depends on Gen. v2: use yet another better name (Chris) Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20170809212603.28780-1-michal.wajdeczko@intel.comReviewed-by:
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Chris Wilson authored
When switching between contexts using the aliasing_ppgtt, the VM is shared. We don't need to reload the PD registers unless they are dirty. Martin Peres reported an issue that looks like corruption between Haswell context switches, bisecting to commit f9326be5 ("drm/i915: Rearrange switch_context to load the aliasing ppgtt on first use"). Switching between the same mm (the aliasing_ppgtt is used for all contexts in this case) should be a nop, but appears to trigger some side-effects in the context switch. However, as we know the switch is redundant in this case, we can skip it and continue to ignore the issue until somebody feels strong enough to investigate full-ppgtt on gen7 again! Except.. Martin was using full-ppgtt which is not supported as it doesn't work correctly yet. So whilst the bisect did yield valuable information about the failures, the fix should not have any user impact under default settings, with the exception of a slightly lower throughput on xcs as the VM would always be reloaded. v2: Also remember to set the legacy_active_context following the switch on xcs (commit e8a9c58f ("drm/i915: Unify active context tracking between legacy/execlists/guc")) Fixes: f9326be5 ("drm/i915: Rearrange switch_context to load the aliasing ppgtt on first use") Fixes: e8a9c58f ("drm/i915: Unify active context tracking between legacy/execlists/guc") Reported-by:
Martin Peres <martin.peres@linux.intel.com> Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170812152724.6883-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Since we do use the SW_SYNC in igt for validating dma-fence and sync_file, and wish to expand usage to cover driver independent portions of syncobj interaction, ensure SW_SYNC is included in our testing Kconfig. Signed-off-by:
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- 11 Aug, 2017 7 commits
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Rodrigo Vivi authored
The idea is to have an unique place to decide the pin-port per platform. So let's create this function now without any functional change. Just adding together code from hdmi and dp together. v2: Add missing pin for port A. v3: Fix typo on subject. Avoid behaviour change so add WARN_ON and return if port A on HDMI. (by DK). Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170811182650.14327-2-rodrigo.vivi@intel.com
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Rodrigo Vivi authored
We will soon need to make that pin port association per platform, so let's try to simplify it beforehand. Also we are moving the backwards port to pin here as well so let's use a standardized way. One extra possibility here would be to add a MISSING_CASE along with PORT_NONE, but I don't want to change this behaviour for now. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Rodrigo Vivi authored
Different from SKL we don't need ctrl1 and cfgcr2, but we need to dump cfgcr0 and cfgcr1 instead. v2: rebase and commit message Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170810224525.18278-1-rodrigo.vivi@intel.com
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Rodrigo Vivi authored
"Frequencies over 5.4 GHz only supported on certain DDI ports and SKUs, and requires Vccio >= 0.95V." More specifically, for current CNL SKUs available (CNL-U and CNL-Y) we have: DDI A - 5.4G eDP DDI B - 8.1G DP DDI C - 8.1G DP DDI D - 5.4G DP v2: Rebase on top of source_rates changes. v3: Address the max 5.4 x 8.1 per DDI and also consider vccio. Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170810224008.15571-1-rodrigo.vivi@intel.com
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Matthias Kaehlcke authored
For 0.85V cnl_get_buf_trans_edp() returns the DP table, instead of EDP. Use the correct table. The error was pointed out by this clang warning: drivers/gpu/drm/i915/intel_ddi.c:392:39: warning: variable 'cnl_ddi_translations_edp_0_85V' is not needed and will not be emitted [-Wunneeded-internal-declaration] static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { Fixes: cf54ca8b ("drm/i915/cnl: Implement voltage swing sequence.") Signed-off-by:Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
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Colin Ian King authored
The structure intel_sprite_plane_funcs is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: symbol 'intel_sprite_plane_funcs' was not declared. Should it be static? Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20170811134938.4183-1-colin.king@canonical.com
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Daniel Vetter authored
In our snb farm in CI we have plenty of underruns, but not enough stolen memory to enable fbc. Which means every time there's an underrun the no_fbc_reason swichtes to something that makes kms_frontbuffer_tracking fail instead of skip, adding massive amounts of additional noise to igt test runs. Make sure we don't try to disable fbc when it's off already. v2: Squash in additional WARN_ON suggestion from Chris. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
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- 10 Aug, 2017 18 commits
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Rodrigo Vivi authored
A missing part to EU slice power gating is the debugfs interface. This patch actually should have been squashed to the initial EU slice power gating one. v2: Initial patch was merged without this part. Fixes: c7ae7e9a ("drm/i915/cnl: Configure EU slice power gating.") Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by:
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Paulo Zanoni authored
Gen 10 is just like Gen 9, so let's consider that all the future platforms are going to be like gen 9 instead of being like gen8-. Cc: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Paulo Zanoni authored
A previous commit added CNL to intel_has_sagv(), but forgot to adjust the SAGV block time to gen 10 platforms. Cc: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
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Rodrigo Vivi authored
For now inherit from previous platforms. v2: Rebase on top of CFL. Cc: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Paulo Zanoni authored
Gen 10 should use the exact same code as Gen 9, so change the check to take this into consideration, and also assume that future platforms will run this code. Also add a MISSING_CASE(), just in case we do something wrong, instead of silently failing. Cc: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
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Rodrigo Vivi authored
I'm not sure if this is really the case and I don't believe this is the real fix for the bug mentioned here, but since I don't see a reliable path when mst_port is set and when mode_valid is requested I believe it is worth to have this protection here. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102022 Cc: Elizabeth <elizabethx.de.la.torre.mena@intel.com> Cc: Stefan Assmann <sassmann@redhat.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by:
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Chris Wilson authored
As we cannot have an exclusive stream set if the perf has not been initialized, we only need to check for that exclusive stream. Signed-off-by:
Matthew Auld <matthew.auld@intel.com>
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Chris Wilson authored
This is called from execlist context init which we need to be unlocked. Commit f89823c2 ("drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interface") added a lockdep assert to this path for unclear reasons, remove it again! Fixes: f89823c2 ("drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interface") Signed-off-by:
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Chris Wilson authored
Another case where we need to call sysfs_attr_init() to setup the internal lockdep class prior to use: [ 9.325229] BUG: key ffff880168bc7bb0 not in .data! [ 9.325240] DEBUG_LOCKS_WARN_ON(1) [ 9.325250] ------------[ cut here ]------------ [ 9.325280] WARNING: CPU: 1 PID: 275 at kernel/locking/lockdep.c:3156 lockdep_init_map+0x1b2/0x1c0 [ 9.325301] Modules linked in: intel_powerclamp(+) coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel i915(+) snd_hda_intel snd_hda_codec snd_hwdep r8169 mii snd_hda_core snd_pcm prime_numbers i2c_hid pinctrl_geminilake pinctrl_intel [ 9.325375] CPU: 1 PID: 275 Comm: modprobe Not tainted 4.13.0-rc4-CI-Trybot_1040+ #1 [ 9.325395] Hardware name: Intel Corp. Geminilake/GLK RVP2 LP4SD (07), BIOS GELKRVPA.X64.0045.B51.1704281422 04/28/2017 [ 9.325422] task: ffff8801721a4ec0 task.stack: ffffc900001dc000 [ 9.325440] RIP: 0010:lockdep_init_map+0x1b2/0x1c0 [ 9.325456] RSP: 0018:ffffc900001dfa10 EFLAGS: 00010282 [ 9.325473] RAX: 0000000000000016 RBX: ffff880168d54b80 RCX: 0000000000000000 [ 9.325488] RDX: 0000000080000001 RSI: 0000000000000001 RDI: ffffffff810f0800 [ 9.325505] RBP: ffffc900001dfa30 R08: 0000000000000001 R09: 0000000000000000 [ 9.325521] R10: 0000000000000000 R11: 0000000000000000 R12: ffff880168bc7bb0 [ 9.325537] R13: 0000000000000000 R14: ffff880168bc7b98 R15: ffffffff81a263a0 [ 9.325554] FS: 00007fb60c3fd700(0000) GS:ffff88017fc80000(0000) knlGS:0000000000000000 [ 9.325574] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 9.325588] CR2: 0000006582777d80 CR3: 000000016d818000 CR4: 00000000003406e0 [ 9.325604] Call Trace: [ 9.325618] __kernfs_create_file+0x76/0xe0 [ 9.325632] sysfs_add_file_mode_ns+0x8a/0x1a0 [ 9.325646] internal_create_group+0xea/0x2c0 [ 9.325660] sysfs_create_group+0x13/0x20 [ 9.325737] i915_perf_register+0xde/0x220 [i915] [ 9.325800] i915_driver_load+0xa77/0x16c0 [i915] [ 9.325863] i915_pci_probe+0x37/0x90 [i915] [ 9.325880] pci_device_probe+0xa8/0x130 [ 9.325894] driver_probe_device+0x29c/0x450 [ 9.325908] __driver_attach+0xe3/0xf0 [ 9.325922] ? driver_probe_device+0x450/0x450 [ 9.325935] bus_for_each_dev+0x62/0xa0 [ 9.325948] driver_attach+0x1e/0x20 [ 9.325960] bus_add_driver+0x173/0x270 [ 9.325974] driver_register+0x60/0xe0 [ 9.325986] __pci_register_driver+0x60/0x70 [ 9.326044] i915_init+0x6f/0x78 [i915] [ 9.326066] ? 0xffffffffa024e000 [ 9.326079] do_one_initcall+0x43/0x170 [ 9.326094] ? rcu_read_lock_sched_held+0x7a/0x90 [ 9.326109] ? kmem_cache_alloc_trace+0x261/0x2d0 [ 9.326124] do_init_module+0x5f/0x206 [ 9.326137] load_module+0x2561/0x2da0 [ 9.326150] ? show_coresize+0x30/0x30 [ 9.326165] ? kernel_read_file+0x105/0x190 [ 9.326180] SyS_finit_module+0xc1/0x100 [ 9.326192] ? SyS_finit_module+0xc1/0x100 [ 9.326210] entry_SYSCALL_64_fastpath+0x1c/0xb1 [ 9.326223] RIP: 0033:0x7fb60bf359f9 [ 9.326234] RSP: 002b:00007fff92b47c48 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 [ 9.326255] RAX: ffffffffffffffda RBX: ffffffff814898a3 RCX: 00007fb60bf359f9 [ 9.326271] RDX: 0000000000000000 RSI: 00000028a9ceef8b RDI: 0000000000000000 [ 9.326287] RBP: ffffc900001dff88 R08: 0000000000000000 R09: 0000000000000000 [ 9.326303] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000040000 [ 9.326319] R13: 00000028aaef2a70 R14: 0000000000000000 R15: 00000028aaeee5d0 [ 9.326339] ? __this_cpu_preempt_check+0x13/0x20 [ 9.326353] Code: f1 39 00 85 c0 0f 84 38 ff ff ff 83 3d 9f 44 ce 01 00 0f 85 2b ff ff ff 48 c7 c6 b2 a2 c7 81 48 c7 c7 53 40 c5 81 e8 3f 82 01 00 <0f> ff e9 11 ff ff ff 0f 1f 80 00 00 00 00 55 31 c9 31 d2 31 f6 Fixes: 701f8231 ("drm/i915/perf: prune OA configs") Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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Jani Nikula authored
This is not to try to force a new style; this is my interpretation of what the most common existing style is. With hopes I don't need to answer so many questions about style going forward. Start a new style section in the i915 document to bolt the register style guide into. v2: vertical alignment, incorporate to kernel-doc, and more Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/9de4a5b1bea4e76461c70a1dd66751581de0124f.1502368010.git.jani.nikula@intel.com
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Jani Nikula authored
Revert to a normal comment, as the enum isn't properly documented anyway. Signed-off-by:
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Jani Nikula authored
Remove old warning about docproc directive that's not supported in the Sphinx toolchain. Signed-off-by:
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Ben Widawsky authored
This was based on a patch originally by Kristian. It has been modified pretty heavily to use the new callbacks from the previous patch. v2: - Add LINEAR and Yf modifiers to list (Ville) - Combine i8xx and i965 into one list of formats (Ville) - Allow 1010102 formats for Y/Yf tiled (Ville) v3: - Handle cursor formats (Ville) - Put handling for LINEAR in the mod_support functions (Ville) v4: - List each modifier explicitly in supported modifiers (Ville) - Handle the CURSOR plane (Ville) v5: - Split out cursor and sprite handling (Ville) v6: - Actually use the sprite funcs (Emil) - Use unreachable (Emil) v7: - Only allow Intel modifiers and LINEAR (Ben) v8 - Fix spite assert introduced in v6 (Daniel) v9 - Change vendor check logic to avoid magic 56 (Emil) - Reorder skl_mod_support (Ville) - make intel_plane_funcs static, could be done as of v5 (Ville) - rename local variable intel_format_modifiers to modifiers (Ville) - actually use sprite modifiers - split out modifier/formats by platform (Ville) v10: - Undo vendor check from v9 v11: - Squash CCS advertisement into this patch (daniels) - Don't advertise CCS on higher sprite planes (daniels) v12: - Don't advertise Y-tiled or CCS on any sprite planes, since we don't allocate enough DDB space for it to work. (daniels) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> (v8) Signed-off-by:Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
Daniel Stone <daniels@collabora.com>
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Ville Syrjälä authored
SKL+ display engine can scan out certain kinds of compressed surfaces produced by the render engine. This involved telling the display engine the location of the color control surfae (CCS) which describes which parts of the main surface are compressed and which are not. The location of CCS is provided by userspace as just another plane with its own offset. Add the required stuff to validate the user provided AUX plane metadata and convert the user provided linear offset into something the hardware can consume. Due to hardware limitations we require that the main surface and the AUX surface (CCS) be part of the same bo. The hardware also makes life hard by not allowing you to provide separate x/y offsets for the main and AUX surfaces (excpet with NV12), so finding suitable offsets for both requires a bit of work. Assuming we still want keep playing tricks with the offsets. I've just gone with a dumb "search backward for suitable offsets" approach, which is far from optimal, but it works. Also not all planes will be capable of scanning out compressed surfaces, and eg. 90/270 degree rotation is not supported in combination with decompression either. This patch may contain work from at least the following people: * Vandana Kannan <vandana.kannan@intel.com> * Daniel Vetter <daniel@ffwll.ch> * Ben Widawsky <ben@bwidawsk.net> v2: Deal with display workarounds 0390, 0531, 1125 (Paulo) v3: Pretend CCS tiles are regular 128 byte wide Y tiles (Jason) Put the AUX register defines to the correct place Fix up the slightly bogus rotation check v4: Use I915_WRITE_FW() due to plane update locking changes s/return -EINVAL/goto err/ in intel_framebuffer_init() Eliminate a bunch hardcoded numbers in CCS code v5: (By Ben) conflict resolution + - res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum); + res_blocks += fixed16_to_u32_round_up(y_tile_minimum); v6: (daniels) Fix botched commit message. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by:Ville Syrjä <ville.syrjala@linux.intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (v1) Reviewed-by:
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Ville Syrjälä authored
SKL+ display engine can scan out certain kinds of compressed surfaces produced by the render engine. This involved telling the display engine the location of the color control surfae (CCS) which describes which parts of the main surface are compressed and which are not. The location of CCS is provided by userspace as just another plane with its own offset. By providing our own format information for the CCS formats, we should be able to make framebuffer_check() do the right thing for the CCS surface as well. Note that we'll return the same format info for both Y and Yf tiled format as that's what happens with the non-CCS Y vs. Yf as well. If desired, we could potentially return a unique pointer for each pixel_format+tiling+ccs combination, in which case we immediately be able to tell if any of that stuff changed by just comparing the pointers. But that does sound a bit wasteful space wise. v2: Drop the 'dev' argument from the hook v3: Include the description of the CCS surface layout v4: Pretend CCS tiles are regular 128 byte wide Y tiles (Jason) v5: Re-drop 'dev', fix commit message, add missing drm_fourcc.h description of CCS layout. (daniels) Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Acked-by:Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (v3) Reviewed-by:
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Daniel Vetter authored
Ben Widawsky/Daniel Stone need the extended modifier support from drm-misc to be able to merge CCS support for i915.ko Signed-off-by: -
Chris Wilson authored
In the original selftest, we didn't care what the engine->id was, just that it could uniquely identify it. Later though, we started tracking the mock engines in the fixed size arrays around the drm_i915_private and so we now require their indices to be correct. This becomes an issue when using the standalone harness which runs all available tests at module load, and so we quickly assign an out-of-bounds index to an engine as we reallocate the mock GEM device between tests. It doesn't show up in igt/drv_selftest as that runs each subtest individually. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102045Signed-off-by:
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git://anongit.freedesktop.org/git/drm-miscDave Airlie authored
UAPI Changes: - vc4: Add ioctl to allow attaching a label to a bo (Eric) - Add new format/modifier blob plane property (Ben) - armada: Use __u32/__u64 instead of uint32_t/uint64_t (Mikko) - [kinda uapi] fb_helper: Expose display_info size via fb_info (David) Core Changes: - Default gem_dumb_[map_offset|destroy] as mmap/destroy implementations (Noralf) - Simplify atomic properties by removing the helpers and handling in core (Daniel) Driver Changes: - stm: Add STM32 DSI controller driver (Phillipe) - vc4: Add HDMI CEC support (Hans) - rockchip: Refactor register init & soc version handling (Mark) - misc: Remove .load_lut, .gamma_set, .gamma_get dead code (Peter) - dw-hdmi: Add HDMI CEC support (Russell) Cc: Philippe CORNU <philippe.cornu@st.com> Cc: Hans Verkuil <hans.verkuil@cisco.com> Cc: Eric Anholt <eric@anholt.net> Cc: Noralf Trønnes <noralf@tronnes.org> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Mark yao <mark.yao@rock-chips.com> Cc: Peter Rosin <peda@axentia.se> Cc: Russell King <rmk+kernel@armlinux.org.uk> Cc: Mikko Rapeli <mikko.rapeli@iki.fi> Cc: David Lechner <david@lechnology.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> * tag 'drm-misc-next-2017-08-08' of git://anongit.freedesktop.org/git/drm-misc: (107 commits) drm: Nuke drm_atomic_legacy_backoff drm: Nuke drm_atomic_helper_connector_dpms drm: Nuke drm_atomic_helper_connector_set_property drm: Nuke drm_atomic_helper_plane_set_property drm: Nuke drm_atomic_helper_crtc_set_property drm: Handle properties in the core for atomic drivers drm: Don't update property values for atomic drivers drm/omap: Rework the rotation-on-crtc hack drm/radeon: Use the drm_driver.dumb_destroy default drm/i915: Use the drm_driver.dumb_destroy default drm/sti: Use .dumb_map_offset and .dumb_destroy defaults drm: bridge: synopsys/dw-hdmi: Provide default configuration function for HDMI 2.0 PHY drm/fb-helper: pass physical dimensions to fbdev uapi drm/armada_drm.h: use __u32 and __u64 instead of uint32_t and uint64_t drm/bridge: dw-hdmi: remove CEC engine register definitions drm/bridge: dw-hdmi: add cec driver drm/bridge: dw-hdmi: add missing cec_notifier_put drm: remove unused and redundant callbacks staging: vboxvideo: remove dead gamma lut code drm: dw-hdmi-i2s: add missing company name on Copyright ...
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- 09 Aug, 2017 1 commit
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Jim Bride authored
Bit 29 of SRD_CTL needs to have its value preserved according to the B-Spec, so right before we write out the register we go ahead and read the register and preserve the value of that bit before we write out the configured register value. v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Jim Bride <jim.bride@linux.intel.com> Reviewed-by:
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- 08 Aug, 2017 8 commits
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Rodrigo Vivi authored
DDI_E is not supported on CNL-U and CNL-Y When adding the initial support we noticed DDI_E wasn't supported and removed it on v4 and v5 of that patch. However for some reason I missed or put back these 2 chunks. Time to clean it up to avoid later confusion. Fixes: 8bcd3dd4 ("drm/i915/cnl: Add power wells for CNL") Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170808193237.17410-1-rodrigo.vivi@intel.com
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Chris Wilson authored
As we may have just bound the renderstate into the GGTT for execution, we need to ensure that the GTT TLB are also flushed. On snb-gt2, this would cause a random GPU hang at the start of a new context (e.g. boot) and on snb-gt1, it was causing the renderstate batch to take ~10s. It was the GPU hang that revealed the truth, as the CS gleefully executed beyond the end of the golden renderstate batch, a good indicator for a GTT TLB miss. Fixes: 20fe17aa ("drm/i915: Remove redundant TLB invalidate on switching contexts") Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: <drm-intel-fixes@lists.freedesktop.org> # v4.12-rc1+
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Daniel Vetter authored
Finally all users are gone! Reviewed-by:
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Daniel Vetter authored
It's dead code, the core handles all this directly now. The only special case is nouveau and tda988x which used one function for both legacy modeset code and -nv50 atomic world instead of 2 vtables. But amounts to exactly the same. v2: Rebase over the panel/brideg refactorings in stm/ltdc. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de> Acked-by:
Archit Taneja <architt@codeaurora.org> Tested-by: Philippe Cornu <philippe.cornu@st.com> (on stm) Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by:
Shawn Guo <shawnguo@kernel.org> Acked-by:
Noralf Trønnes <noralf@tronnes.org> Acked-by:
Vincent Abriou <vincent.abriou@st.com>
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Daniel Vetter authored
It's dead code, the core handles all this directly now. This also allows us to unexport drm_atomic_helper_connector_set_property. The only special case is nouveau which used one function for both pre-nv50 legacy modeset code and post-nv50 atomic world instead of 2 vtables. But amounts to exactly the same. What is rather strange here is how few drivers set this up, I suspect the earlier patch to handle properties in the core did end up fixing a pile of possible issues. Signed-off-by:
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Daniel Vetter authored
It's dead code, the core handles all this directly now. This also allows us to unexport drm_atomic_plane_set_property. Signed-off-by:
Philippe Cornu <philippe.cornu@st.com> Tested-by:
Liviu Dudau <Liviu.Dudau@arm.com> Acked-by:
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Daniel Vetter authored
It's dead code because this is now handled in the core. Signed-off-by:
Thomas Hellstrom <thellstrom@vmware.com>
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Daniel Vetter authored
The reason behind the original indirection through the helper functions was to allow existing drivers to overwrite how they handle properties. For example when a vendor-specific userspace had expectations that didn't match atomic. That seemed likely, since atomic is standardizing a _lot_ more of the behaviour of a kms driver. But 20 drivers later there's no such need at all. Worse, this forces all drivers to hook up the default behaviour, breaking userspace if they forget to do that. And it forces us to export a bunch of core function just for those helpers. And finally, these helpers are the last places using drm_atomic_legacy_backoff() and the implicit acquire_ctx. This patch here just implements the new behaviour and updates the docs. Follow-up patches will garbage-collect all the dead code. v2: Fixup docs even better! v3: Make it actually work ... v4: Drop the uses_atomic_modeset() checks from the previous patch again, since they're now moved up in the callchain. Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Archit Taneja <architt@codeaurora.org> (v3) Reviewed-by:
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