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- 30 Mar, 2017 20 commits
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Alex Deucher authored
There will be a slightly different version for atomfirmware. Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Ken Wang <Qingqing.Wang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tom St Denis authored
Forces VCE/UVD off during late init to ensure they're powered off correctly during boot. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Samuel Li <Samuel.Li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Newer asics use different registers so abstract it. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rex Zhu authored
v2: agd: integrate Christian's comments. v3: print error message if call fails Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Ken Wang authored
Newer asics need 64 bit doorbells. v2: fix comment (Nils) Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Ken Wang <Qingqing.Wang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Ken Wang authored
Newer asics need 64 bit writeback slots. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Ken Wang <Qingqing.Wang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Not used in a while. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Ken Wang <Qingqing.Wang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Joe Perches authored
Use a more common logging style. Miscellanea: o Coalesce formats and realign arguments o Neaten a few macros now using pr_<level> Signed-off-by:
Joe Perches <joe@perches.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
There still seem to be some blocks that make accesses in the lower part of the address space. This works around this. Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
v2: use in_rest to fix compute ring test failure issue which occured after FLR/gpu_reset. we need backup a clean status of MQD which was created in drv load stage, and use it in resume stage, otherwise KCQ and KIQ all may faild in ring/ib test. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
some registers are PF & VF copy, and we can safely use mmio method to access them. and sometime we are forbid to use kiq to access registers for example in INTR context. we need a MACRO that always disable KIQ for regs accessing Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Samuel Pitoiset authored
read_sensor() has been recently implemented for dpm based boards which means amdgpu_sensors can now be exposed. v2: - make sure read_sensor is not NULL on dpm chips - keep sanity check for powerplay chips v3: - make sure amdgpu_dpm != 0 Cc: Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tom St Denis authored
This update allows sensors to return more than 1 value and indicates to the caller how many bytes are written. The debugfs interface has been updated to handle reading all of the values. Simply seek to the enum value (multiplied by 4) and then read as many bytes as the sensor provides. (v2): Don't set size to 4 before reading GPU_POWER (v3): agd: rebase Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
no suspend invoked so after VF FLR by host, we just call hw_init to reinitialize IPs. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
this lock is used for sriov_gpu_reset, only get this mutex can run into sriov_gpu_reset. we have couple source triggers gpu_reset for SRIOV: 1) submit timedout and trigger reset voluntarily 2) invalid instruction detected by ENGINE and trigger reset voluntarily 2) hypervisor found world switch hang and trigger flr and notify guest to do reset. all need take care and we need a mutex to protect the consistency of reset routine. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
implement SRIOV gpu_reset for future use. it wil be called from: 1) job timeout 2) privl access or instruction error interrupt 3) hypervisor detect VF hang v2: agd: rebase on upstream Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
ib_pool init should prior to fbdev_init, otherwise there will be error from amdgpu_sa_bo_new (amdgpu_sa.c:323) fbdev_init will call ttm_validate which further call amdgpu_sa_bo_new. v2: move fbdev_init behind ib test. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 16 Mar, 2017 1 commit
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Huang Rui authored
The clearing wb size should be the one that it is assigned. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 15 Mar, 2017 1 commit
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Tom St Denis authored
The MMIO space is wider now so we mask the lower 22 bits instead of 18. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 08 Mar, 2017 1 commit
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Jim Qu authored
Signed-off-by:
Jim Qu <Jim.Qu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 17 Feb, 2017 1 commit
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Jim Qu authored
Check whether we need to post rather than whether the asic is posted. There are some cases (e.g., GPU reset or resume from hibernate) where we need to force post even if the asic has been posted. Signed-off-by:
Jim Qu <Jim.Qu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 27 Jan, 2017 12 commits
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Yintian Tao authored
In the case of pass-through, amdgpu.ko may be included into a image with the hard code ID therefore loading driver with specified virtual display ID will lose efficacy when the BDF of GPU modifies.So add the new ID string "all" for it as same as vf case what does. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Yintian Tao <yttao@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Xiangliang Yu authored
Reboot process will call HW fini functions of IP blocks. For virt, need to send event three before hw fini and send event four after hw fini. Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tom St Denis authored
So we can determine which device the entry is before connecting a display. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Xiangliang Yu authored
Current amdgpu reset process only works on bare-metal and for SRIOV many inside it need re-work to adapt to vf device. This is a temporary workaround to skip gpu reset. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Xiangliang Yu authored
For gpu vf device, first need to request full gpu access before accessing gpu registers, and release full gpu access after the access is done. Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Xiangliang Yu authored
For virtualization, it is must for driver to use KIQ to access registers when it is out of GPU full access mode. v2: agd: rebase Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Monk Liu <Monk.Liu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
Make sure the CSA is mapped. v2: agd: rebase. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Huang Rui authored
Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Xiangliang Yu authored
Use acronym to rename fields to make easy to spell out. Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Amber Lin authored
PCI I/O bar can be disabled in VBIOS to save the resource. It is often disabled in large aperture VBIOS. Don't call it an error. Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nils Wallménius authored
This is a left over from radeon, amdgpu doesn't support any non-atombios parts and amdgpu_device_init would bail if the check for atombios failed anyway. Reviewed-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by:
Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Noralf Trønnes authored
drm_debugfs_cleanup() now removes all minor->debugfs_list entries automatically, so no need to call drm_debugfs_remove_files(). Also remove empty drm_driver.debugfs_cleanup callback. Cc: alexander.deucher@amd.com Cc: christian.koenig@amd.com Signed-off-by:
Noralf Trønnes <noralf@tronnes.org> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170126225621.12314-5-noralf@tronnes.org
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- 06 Jan, 2017 1 commit
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Junwei Zhang authored
v2: agd: squash in various fixes v3: agd: squash in: drm/amdgpu: remove unnecessary smc sk firmware for polaris12 Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Ken Wang <Qingqing.Wang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 08 Dec, 2016 1 commit
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Tom St Denis authored
Implemented for SGPRs for GFX v8 initially. (v2) cleanup minor whitespace and remove sanity check and addressing is in dwords not bytes Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Acked-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 07 Dec, 2016 1 commit
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Alex Deucher authored
We can't just reuse pci_remove as there may be userspace still doing things. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98638 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97980Reviewed-by:
Christian König <christian.koenig@amd.com> Reported-and-tested-by:
Mike Lothian <mike@fireburn.co.uk> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 06 Dec, 2016 1 commit
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Rex Zhu authored
Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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