Merge "Second part of X-Gene DT changes queued for v4.6" from Duc Dang:

This patch set includes:
+ X-Gene v2 Mailbox DT node
+ X-Gene v1 and X-Gene v2 SLIMpro Mailbox
I2C driver DT nodes

* tag 'xgene-dts-for-v4.6-part2' of https://github.com/AppliedMicro/xgene-next:
  arm64: dts: apm: Add DT node for X-Gene v2 SLIMpro Mailbox I2C Driver
  arm64: dts: apm: Mailbox device tree node for APM X-Gene v2 platform.
  arm64: dts: apm: Add DT node for X-Gene v1 SLIMpro Mailbox I2C Driver
  arm64: dts: apm: mailbox device tree node for APM X-Gene platform.

Merge "First part of X-Gene DT changes queued for v4.6" from Duc Dang:

This patch set includes:
+ A change in compatible string of X-Gene v2 SoC
PLL DT node to reflect the v2 hardware
+ Update DT fields for X-Gene v1 and v2 standby
GPIO controllers
+ Update declaration of power button GPIO for
X-Gene v1 and X-Gene v2 platforms

* tag 'xgene-dts-for-v4.6-part1' of https://github.com/AppliedMicro/xgene-next:
  arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms
  arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platforms
  arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms
  arm64: dts: apm: Update X-Gene standby GPIO controller DTS entries
  arm64: dts: apm: Update Merlin DT PCP PLL clock node for v2 hardware

Merge "ARM64: DT: Hisilicon Hip05 soc and D02 board updates for 4.6" from Wei Xu:

- Add L2 cache topology
- Use Cortex specific device node for pmu
- Append all gicv3 ITS entries
- Append gpio nodes
- Append power button node for D02 board

* tag 'hip05-dt-for-4.6' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hip05: Append power button node for D02 board
  arm64: dts: hip05: Append gpio nodes
  arm64: dts: hip05: Append all gicv3 ITS entries
  arm64: dts: hip05: Use Cortex specific device node for pmu
  arm64: dts: hip05: Add L2 cache topology

Merge tag 'renesas-arm64-dt2-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Merge "Second Round of Renesas ARM64 Based SoC DT Updates for v4.6"
from Simon Horman:

Updates for r8a7795/salvator-x
* Enable USB2.0, and SDHI0 & 3
* Add GIC-400 virtual interfaces
* Add INTC-EX and L2 cache-controller nodes
* Use fallback etheravb compatibility string
* Use GIC_* defines where appropriate

* tag 'renesas-arm64-dt2-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: salvator-x: enable USB 2.0 Host of channel 1 and 2
  arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2
  arm64: dts: r8a7795: add USB2.0 Host (EHCI/OHCI) device nodes
  arm64: dts: r8a7795: add usb2_phy device nodes
  arm64: dts: r8a7795: use fallback etheravb compatibility string
  arm64: dts: r8a7795: salvator-x: enable SDHI0 & 3
  arm64: dts: r8a7795: Add SDHI support to dtsi
  arm64: dts: r8a7795: Add GIC-400 virtual interfaces
  arm64: dts: r8a7795: Add INTC-EX device node
  arm64: dts: r8a7795: Add CA53 L2 cache-controller node
  arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node
  arm64: dts: r8a7795: use GIC_* defines
  arm64: dts: r8a7795: pmu: switch to Cortex specific device nodes
  arm64: dts: r8a7795: Add L2 cache-controller nodes

Merge "Broadcom devicetree-arm64 changes for 4.6" from Florian Fainelli:

This pull request contains Broadcom ARM64-based SoCs device tree changes:

- Anup adds additional nodes to the Broadcom Northstart 2 Device Trees: SDHCI
  (iProc-compatible), ARM SP804 timers, ARM SP805 watchdog

- Anup also adds a binding documentation for the ARM SP805 watchdog since there
  was not one in tree before

- Ray adds PCIE root complex nodes to the Northstar 2 Device Tree nodes, using
  the iProc-compatible binding

- Jayachandran C. adds binding documentation for the Broadcom Vulcan processors and
  reference platforms

* tag 'arm-soc/for-4.6/devicetree-arm64' of http://github.com/Broadcom/stblinux:
  dt-bindings: Add documentation for Broadcom Vulcan
  arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2
  arm64: dts: Add ARM SP805 watchdog DT node for NS2
  dt-bindings: watchdog: Add ARM SP805 DT bindings
  arm64: dts: Add ARM SP804 timer DT nodes for NS2
  arm64: dts: Add SDHCI DT node for NS2

Following the addition of the Alpine MSIX controller driver, add the
corresponding node in the Alpine v2 device tree.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This patch adds the initial support for the Alpine v2 EVP board from
Annapurna Labs (Amazon).
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Barak Wasserstrom <barak@annapurnalabs.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge "ARM: Xilinx ZynqMP dt patches for v4.6" from Michal Simek:

- Extract clock information from EP108
- Sort GPIO node

* tag 'zynqmp-dt-for-4.6' of https://github.com/Xilinx/linux-xlnx:
  ARM64: zynqmp: Extract clock information from EP108
  ARM64: zynqmp: Keep gpio node alphabetically sorted

Merge "ARM: mediatek: dts updates for v4.6" from Matthias Brugger:

Add nor-flash to mt8173 SoC.
Add efuse device to mt8173 SoC.
Fix power-domain issue mt8173-evb which uses older chip revision.

* tag 'v4.5-next-dts64' of https://github.com/mbgg/linux-mediatek:
  ARM64: dts: Mediatek: mt8173-evb: fix access MMC fail issue
  dts: arm64: Add EFUSE device node
  arm64: dts: mt8173: Add nor flash node

Add DT node to enable SLIMpro Mailbox I2C Driver for
X-Gene v2 platforms.
Signed-off-by: Duc Dang <dhdang@apm.com>

Add mailbox device tree node for APM X-Gene v2 platform.
Signed-off-by: Duc Dang <dhdang@apm.com>

Add DT node to enable SLIMpro Mailbox I2C Driver for
X-Gene v1 platforms.
Signed-off-by: Duc Dang <dhdang@apm.com>

Mailbox device tree node for APM X-Gene platform.
Signed-off-by: Feng Kan <fkan@apm.com>
Signed-off-by: Duc Dang <dhdang@apm.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

This patch updates gpio-keys node that supports power-off for
X-Gene v2 Merlin board to adapt with new changes in xgene-gpio-sb
driver (to support configuring some GPIO pins as interrupt pins).
Signed-off-by: Quan Nguyen <qnguyen@apm.com>
Signed-off-by: Duc Dang <dhdang@apm.com>

xgene-gpio-sb driver now supports configuring some GPIO pins
as interrupt pins. This patch adds the required fields for GPIO
standby controller DT node of X-Gene v2 platform to work with
this new driver change.
Signed-off-by: Quan Nguyen <qnguyen@apm.com>
Signed-off-by: Duc Dang <dhdang@apm.com>

This patch updates gpio-keys node that supports power-off for
X-Gene v1 Mustang board to adapt with new changes in xgene-gpio-sb
driver (to support configuring some GPIO pins as interrupt pins).
Signed-off-by: Duc Dang <dhdang@apm.com>

We should set SW15 to pin 2-3 side on the board before we use CN9
as USB host or peripheral.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This board has a MAX3355 chip. However, we cannot use the extcon/max3355
driver because the ID pin doesn't connect to a gpio pin (in other words,
it connects to the SoC specific pin).
And, the phy-rcar-gen3-usb2 driver cannot handle such a chip for now.
So, this patch enables usb2_phy of channel 1 and 2.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Use recently added fallback compatibility string in r8a7795 device tree.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>

Add the exposed SD card slots. The on-board eMMC needs to wait until we
fixed the 8bit support.
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[wsa: squashed some fixes and added mmc-caps]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Update APM X-Gene standby GPIO controller DTS entries to enable it
as interrupt controller.

[dhdang: update patch subject]
Signed-off-by: Y Vo <yvo@apm.com>
Signed-off-by: Quan Nguyen <qnguyen@apm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Duc Dang <dhdang@apm.com>

Update Merlin DT PCP PLL clock node to reflect compatible
string change to reflect v2 hardware.

[dhdang: change patch subject]
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Duc Dang <dhdang@apm.com>

This patch adds poweroff button device node to support
poweroff feature on hip05 d02 board.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

There are two dw GPIO controllers in hip05 peri sub, this patch
adds the corresponding device tree nodes.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

There are four subsystems in hip05 soc, peri/m3/pcie/dsa,
each subsystem has one its, append them under gicv3 node.

They will be used by hisilicon mbigen.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Instead of using the generic armv8-pmuv3 compatibility, use
the more specific Cortex A57 compatibility.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus
share one L2 cache, add them to the dtsi file so that the cache
hierarchy can be probed.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Extract clocks and put it specific file to help with platform
autogeneration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

No functional change.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

mvebu dt64 for 4.6 (part 1)

Device tree part of the Armada 3700 support:
- binding for the Armada 3700 SoCs
- device tree files for the SoCs and a board
- tidy up the Marvell related files

* tag 'mvebu-dt64-4.6-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: add the Marvell Armada 3700 family and a development board
  devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC family
  Documentation: dt: Tidy up the Marvell related files
  Documentation: dt-bindings: Add a new compatible for the Armada 3700
Signed-off-by: Olof Johansson <olof@lixom.net>

This is a fix-up patch based on the review comment from
Arnd regarding:
    * fix ccn504 address in the node name
    * remove kcs interrupt-name
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'v4.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

Define the tuning-related mmc clocks and move from
gpio-key,wakeup to the more generic wakeup-source property.

* tag 'v4.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: replace gpio-key,wakeup with wakeup-source property
  arm64: dts: rockchip: add rk3368 tuning clk for emmc and sdmmc
Signed-off-by: Olof Johansson <olof@lixom.net>

Update arm/cpus.txt to add "brcm,vulcan" CPU. Add documentation
for Broadcom Vulcan boards in arm/bcm/brcm,vulcan-soc.txt
Signed-off-by: Jayachandran C <jchandra@broadcom.com>

MT8173 E1 chip has one bug that if turn off USB power domain, vcore
power will also be off, thus cause modules using vcore power domain
fail, like MMC. The E1 chip only found on MT8173-evb board and this
board only has E1 chip, so implement this as a board specific
workaround.

Pwrapper use vcore power, so add pwrapper using USB power domain to
keep USB power domain not to zero and disabled.
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

Besides the distributor and the CPU interface the GIC-400 additionally
supports the virtual interface control blocks and the virtual CPU interfaces.

Add the physical base addresses and size for these.

See

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0471b/index.html
-> 3.2. GIC-400 register map

and Linux kernel's

Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt

for more details.

For the at GICH Virtual interface control blocks at 0xf1040000 cover the
whole 128kB (0x20000) range. This is done based on the advice from Marc
Zyngier http://www.spinics.net/lists/arm-kernel/msg483139.htmlSigned-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Add initial dtsi files to support Marvell Armada 3700 SoC with Cortex-A53
CPUs. There are two members in this family: the Armada 3710 (Single CPU)
and the Armada 3720 (Dual CPUs).

It also adds a dts file for the Marvell Armada 3720 DB board.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

The Marvell Armada 3700 is a family of ARMv8 CA53 SoCs. This commit
introduces the Device Tree binding that documents the top-level
compatible strings for Armada 3700 based platforms.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>