- 21 Jan, 2023 3 commits
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Dmitry Baryshkov authored
Rewrite dpu_hw_ctl_setup_blendstage() to use static data configuration rather than using a switch-case. This simplifies adding support for new pipes. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550 Patchwork: https://patchwork.freedesktop.org/patch/518485/ Link: https://lore.kernel.org/r/20230116063316.728496-3-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
Extract the common expression in the dpu_hw_ctl_setup_blendstage() function. Signed-off-by:
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Dmitry Baryshkov authored
SM8550 uses new register to map SSPP_DMA4 and SSPP_DMA5 units to blend stages. Add proper support for this register to allow using these two planes for image processing. Fixes: efcd0107 ("drm/msm/dpu: add support for SM8550") Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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- 18 Jan, 2023 5 commits
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Dmitry Baryshkov authored
According to the vendor dts files, both sc7180 and sc7280 support the source split mode (using two LMs for a single output). Change these two platforms to use MIXER_SDM845_MASK, which includes DPU_MIXER_SOURCESPLIT. Rename MIXER_SC7180_MASK to MIXER_QCM2290_MASK, since this platform doesn't seem to support source split mode. Signed-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/518479/ Link: https://lore.kernel.org/r/20230116034435.569512-1-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
For each CRTC we are creating two different debugfs directories one using crtc index (created automatically for the CRC files) and another one using CRTC name/object ID (for state and status files). This can be confusing, so move our custom files to crtc->debugfs_entry, effetively merging two debugfs dirs. Signed-off-by:
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Marijn Suijten authored
In the event that the topology requests resources that have not been created by the system (because they are typically not represented in dpu_mdss_cfg ^1), the resource(s) in global_state (in this case DSC blocks, until their allocation/assignment is being sanity-checked in "drm/msm/dpu: Reject topologies for which no DSC blocks are available") remain NULL but will still be returned out of dpu_rm_get_assigned_resources, where the caller expects to get an array containing num_blks valid pointers (but instead gets these NULLs). To prevent this from happening, where null-pointer dereferences typically result in a hard-to-debug platform lockup, num_blks shouldn't increase past NULL blocks and will print an error and break instead. After all, max_blks represents the static size of the maximum number of blocks whereas the actual amount varies per platform. ^1: which can happen after a git rebase ended up moving additions to _dpu_cfg to a different struct which has the same patch context. Fixes: bb00a452 ("drm/msm/dpu: Refactor resource manager") Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
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Dmitry Baryshkov authored
Struct dpu_encoder_virt_ops is used to provide several callbacks to the phys_enc backends. However these ops are static and are not supposed to change in the foreseeble future. Drop the indirection and call corresponding functions directly. Signed-off-by:
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Konrad Dybcio authored
Add bindings for the display hardware on SM8150. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
Rob Herring <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/514681/ Link: https://lore.kernel.org/r/20221212093315.11390-1-konrad.dybcio@linaro.orgSigned-off-by:
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- 12 Jan, 2023 25 commits
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Marijn Suijten authored
These DSC blocks on CTL V1 need to set its corresponding PINGPONG block index in a hardware register to configure where to send pixel output to, via the newly-added DPU_DSC_OUTPUT_CTRL feature flag. Signed-off-by:
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Marijn Suijten authored
All V1 CTL blocks (active CTLs) explicitly bind the pixel output from a DSC block to a PINGPONG block by setting the PINGPONG index in a DSC hardware register. Signed-off-by:
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Marijn Suijten authored
Downstream calls this num_enc yet the DSC patches introduced a new num_dsc struct member, leaving num_enc effectively unused. Fixes: 7e9cc175 ("drm/msm/disp/dpu1: Add support for DSC in topology") Signed-off-by:
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Marijn Suijten authored
Resource allocation of DSC blocks should behave more like LMs and CTLs where NULL resources (based on initial hw_blk creation via definitions in the catalog) are skipped ^1. The current hardcoded mapping of DSC blocks however means that resource allocation shouldn't succeed at all when the DSC block on the corresponding index doesn't exist, rather than searching for the next free block. This hardcoded mapping should be loosened separately as DPU 5.0.0 introduced a crossbar where DSC blocks can be "somewhat" freely bound to any PP and CTL (in proper pairs). ^1: which, on hardware that supports DSC, can happen after a git rebase ended up moving additions to _dpu_cfg to a different struct which has the same patch context. Fixes: f2803ee9 ("drm/msm/disp/dpu1: Add DSC support in RM") Signed-off-by:
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Marijn Suijten authored
According to downstream /and the comment copied from it/ this comparison should be the other way around. In other words, when the panel driver requests to use more slices per packet than what could be sent over this interface, it is bumped down to only use a single slice per packet (and strangely not the number of slices that could fit on the interface). Fixes: 08802f51 ("drm/msm/dsi: Add support for DSC configuration") Signed-off-by:
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Marijn Suijten authored
According to downstream the value to use for WORD_COUNT is bytes_per_pkt, which denotes the number of bytes in a packet based on how many slices have been configured by the panel driver times the width of a slice times the number of bytes per pixel. The DSC panels seen thus far use one byte per pixel, only one slice per packet, and a slice width of half the panel width leading to the desired bytes_per_pkt+1 value to be equal to hdisplay/2+1. This however isn't the case anymore for panels that configure two slices per packet, where the value should now be hdisplay+1. Note that the aforementioned panel (on a Sony Xperia XZ3, sdm845) with slice_count=1 has also been tested to successfully accept slice_count=2, which would have shown corrupted output previously. Fixes: 08802f51 ("drm/msm/dsi: Add support for DSC configuration") Signed-off-by:
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Marijn Suijten authored
Active CTLs have to configure what DSC block(s) have to be enabled, and what DSC block(s) have to be flushed; this value was initialized to zero resulting in the necessary register writes to never happen (or would write zero otherwise). This seems to have gotten lost in the DSC v4->v5 series while refactoring how the combination with merge_3d was handled. Fixes: 58dca981 ("drm/msm/disp/dpu1: Add support for DSC in encoder") Signed-off-by:
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Neil Armstrong authored
Add support for the MDSS block on SM8550 platform. Signed-off-by:
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Neil Armstrong authored
Add definitions for the display hardware used on Qualcomm SM8550 platform. Reviewed-by:
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Bjorn Andersson authored
Add compatible for the SC8280XP Mobile Display Subsystem and initialization for version 8.0.0. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/514402/ Link: https://lore.kernel.org/r/20221207220012.16529-4-quic_bjorande@quicinc.comSigned-off-by:
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Bjorn Andersson authored
The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9 interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the necessary definitions and describe the DPU in the SC8280XP. Signed-off-by:
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Bjorn Andersson authored
Add binding for the display subsystem and display processing unit in the Qualcomm SC8280XP platform. Signed-off-by:
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Robert Foss authored
Add compatibles string, "qcom,sm8350-mdss", for the multimedia display subsystem unit used on Qualcomm SM8350 platform. Signed-off-by:
Robert Foss <robert.foss@linaro.org> Reviewed-by:
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Dmitry Baryshkov authored
SM8350 has newer version of DSC blocks, which are not supported by the driver yet. Remove them for now until these blocks are supported by the driver. Signed-off-by:
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Robert Foss authored
Add compatibles string, "qcom,sm8350-dpu", for the display processing unit used on Qualcomm SM8350 platform. Signed-off-by:
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Robert Foss authored
Add compatibility for SM8350 display subsystem, including required entries in DPU hw catalog. Signed-off-by:
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Robert Foss authored
Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for MDSS device tree bindings Signed-off-by:
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Robert Foss authored
Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for DPU device tree bindings Signed-off-by:
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Dmitry Baryshkov authored
Add support for the MDSS block on SM8450 platform. Tested-by:
Vinod Koul <vkoul@kernel.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by:
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Dmitry Baryshkov authored
Add definitions for the display hardware used on Qualcomm SM8450 platform. Tested-by:
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Dmitry Baryshkov authored
On sm8450 a register block was removed from MDP TOP. Accessing it during snapshotting results in NoC errors / immediate reboot. Skip accessing these registers during snapshot. Tested-by:
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Dmitry Baryshkov authored
There is a separate header containing some of MDP TOP register definitions, dpu_hwio.h. Move missing register definitions from dpu_hw_top.c to the mentioned header. Signed-off-by:
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Dmitry Baryshkov authored
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM8450 platform. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Require only properties declared in given schema, which makes the code a bit more readable and easy to follow. Suggested-by:
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Krzysztof Kozlowski authored
The Devicetree bindings document does not have to say in the title that contains "DT properties", but instead just describe the hardware. Signed-off-by:
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- 08 Jan, 2023 3 commits
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Marijn Suijten authored
The mask only describes the `irq_idx % 32` part, making it generally impossible to deduce what interrupt is being enabled/disabled. Since `debug/core_irq` in debugfs (and other prints) also include the full `DPU_IRQ_IDX()` value, print the same full value here for easier correlation instead of only adding the `irq_idx / 32` part. Furthermore, make the dbgstr messages more consistent. Signed-off-by:
Martin Botka <martin.botka@somainline.org> Reviewed-by:
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Hui Tang authored
Because of the possilble failure of devm_kzalloc(), dpu_wb_conn might be NULL and will cause null pointer dereference later. Therefore, it might be better to check it and directly return -ENOMEM. Fixes: 77b001ac ("drm/msm/dpu: add the writeback connector layer") Signed-off-by:
Hui Tang <tanghui20@huawei.com> Reviewed-by:
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Konrad Dybcio authored
SDM845 only has INTF0-3 and has no business caring about the INTF4 irq. Suggested-by:
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- 05 Jan, 2023 4 commits
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Akhil P Oommen authored
As per the downstream driver, gx gbif halt is required only during recovery sequence. So lets avoid it during regular rpm suspend. Signed-off-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/515279/ Link: https://lore.kernel.org/r/20221216223253.1.Ice9c47bfeb1fddb8dc377a3491a043a3ee7fca7d@changeidSigned-off-by:
Rob Clark <robdclark@chromium.org>
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Konrad Dybcio authored
So far the adreno quirks have all been assigned with an OR operator, which is problematic, because they were assigned consecutive integer values, which makes checking them with an AND operator kind of no bueno.. Switch to using BIT(n) so that only the quirks that the programmer chose are taken into account when evaluating info->quirks & ADRENO_QUIRK_... Fixes: 370063ee ("drm/msm/adreno: Add A540 support") Reviewed-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
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Dmitry Baryshkov authored
Fix another oops reproducible when rebooting the board with the Adreno GPU working in the headless mode (e.g. iMX platforms). Unable to handle kernel NULL pointer dereference at virtual address 00000000 when read [00000000] *pgd=74936831, *pte=00000000, *ppte=00000000 Internal error: Oops: 17 [#1] ARM CPU: 0 PID: 51 Comm: reboot Not tainted 6.2.0-rc1-dirty #11 Hardware name: Freescale i.MX53 (Device Tree Support) PC is at msm_atomic_commit_tail+0x50/0x970 LR is at commit_tail+0x9c/0x188 pc : [<c06aa430>] lr : [<c067a214>] psr: 600e0013 sp : e0851d30 ip : ee4eb7eb fp : 00090acc r10: 00000058 r9 : c2193014 r8 : c4310000 r7 : c4759380 r6 : 07bef61d r5 : 00000000 r4 : 00000000 r3 : c44cc440 r2 : 00000000 r1 : 00000000 r0 : 00000000 Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none Control: 10c5387d Table: 74910019 DAC: 00000051 Register r0 information: NULL pointer Register r1 information: NULL pointer Register r2 information: NULL pointer Register r3 information: slab kmalloc-1k start c44cc400 pointer offset 64 size 1024 Register r4 information: NULL pointer Register r5 information: NULL pointer Register r6 information: non-paged memory Register r7 information: slab kmalloc-128 start c4759380 pointer offset 0 size 128 Register r8 information: slab kmalloc-2k start c4310000 pointer offset 0 size 2048 Register r9 information: non-slab/vmalloc memory Register r10 information: non-paged memory Register r11 information: non-paged memory Register r12 information: non-paged memory Process reboot (pid: 51, stack limit = 0xc80046d9) Stack: (0xe0851d30 to 0xe0852000) 1d20: c4759380 fbd77200 000005ff 002b9c70 1d40: c4759380 c4759380 00000000 07bef61d 00000600 c0d6fe7c c2193014 00000058 1d60: 00090acc c067a214 00000000 c4759380 c4310000 00000000 c44cc854 c067a89c 1d80: 00000000 00000000 00000000 c4310468 00000000 c4759380 c4310000 c4310468 1da0: c4310470 c0643258 c4759380 00000000 00000000 c0c4ee24 00000000 c44cc810 1dc0: 00000000 c0c4ee24 00000000 c44cc810 00000000 0347d2a8 e0851e00 e0851e00 1de0: c4759380 c067ad20 c4310000 00000000 c44cc810 c27f8718 c44cc854 c067adb8 1e00: c4933000 00000002 00000001 00000000 00000000 c2130850 00000000 c2130854 1e20: c25fc488 00000000 c0ff162c 00000000 00000001 00000002 00000000 00000000 1e40: c43102c0 c43102c0 00000000 0347d2a8 c44cc810 c44cc814 c2133da8 c06d1a60 1e60: 00000000 00000000 00079028 c2012f24 fee1dead c4933000 00000058 c01431e4 1e80: 01234567 c0143a20 00000000 00000000 00000000 00000000 00000000 00000000 1ea0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 1ec0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 1ee0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 1f00: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 1f20: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 1f40: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 1f60: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 1f80: 00000000 00000000 00000000 0347d2a8 00000002 00000004 00000078 00000058 1fa0: c010028c c0100060 00000002 00000004 fee1dead 28121969 01234567 00079028 1fc0: 00000002 00000004 00000078 00000058 0002fdc5 00000000 00000000 00090acc 1fe0: 00000058 becc9c64 b6e97e05 b6e0e5f6 600e0030 fee1dead 00000000 00000000 msm_atomic_commit_tail from commit_tail+0x9c/0x188 commit_tail from drm_atomic_helper_commit+0x160/0x188 drm_atomic_helper_commit from drm_atomic_commit+0xac/0xe0 drm_atomic_commit from drm_atomic_helper_disable_all+0x1b0/0x1c0 drm_atomic_helper_disable_all from drm_atomic_helper_shutdown+0x88/0x140 drm_atomic_helper_shutdown from device_shutdown+0x16c/0x240 device_shutdown from kernel_restart+0x38/0x90 kernel_restart from __do_sys_reboot+0x174/0x224 __do_sys_reboot from ret_fast_syscall+0x0/0x1c Exception stack(0xe0851fa8 to 0xe0851ff0) 1fa0: 00000002 00000004 fee1dead 28121969 01234567 00079028 1fc0: 00000002 00000004 00000078 00000058 0002fdc5 00000000 00000000 00090acc 1fe0: 00000058 becc9c64 b6e97e05 b6e0e5f6 Code: 15922088 1184421c e1500003 1afffff8 (e5953000) ---[ end trace 0000000000000000 ]--- Fixes: 0a58d2ae ("drm/msm: Make .remove and .shutdown HW shutdown consistent") Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Bryan O'Donoghue authored
There's a typo in describing the core clock as an 'escape' clock. The accurate description is 'core'. Fixes: 4dbe55c9 ("dt-bindings: msm: dsi: add yaml schemas for DSI bindings") Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/515938/ Link: https://lore.kernel.org/r/20221223021025.1646636-4-bryan.odonoghue@linaro.orgSigned-off-by:
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