- 25 Oct, 2016 40 commits
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Christian König authored
This way we can use parse_cs and still keep VM mode enabled. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-and-Tested by: Leo Liu <leo.liu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Rex Zhu authored
Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
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Alex Deucher authored
KV/KB/ML was missed these was implemented for other asics. Acked-by:
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Tom St Denis authored
Add the rest of the basic SQ WAVE fields to finish off the implementation. Eventually, a separate interface will be needed for GPRs. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
Move IP version specific code into a callback. Also add support for gfx7 devices. Signed-off-by:
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Tom St Denis authored
Add PG lock support as well as bank selection to the MMIO write function. Signed-off-by:
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Tom St Denis authored
Allow any of the se/sh/instance fields to be specified as a broadcast by submitting 0x3FF. (v2) Fix broadcast range checking Signed-off-by:
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Tom St Denis authored
On non VI/CZ platforms it would not free the grbm index lock. Reviewed-by:
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Tom St Denis authored
Currently supports CZ/VI. Allows nearly atomic read of wave data from GPU. Signed-off-by:
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Alex Deucher authored
This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tables. This also stored the status information in the same structure. v2: split out spelling fix into a separate patch add a function to add IPs to the list Reviewed-by: -
Alex Deucher authored
and update a comment as well. Reviewed-by:
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Alex Deucher authored
It's not used outside the file. Reviewed-by:
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Alex Deucher authored
Add the proper IP module when requested. Signed-off-by: -
Alex Deucher authored
Returns the vce clock table for the user mode driver. The user mode driver can fill this data into vce clock data packet for optimal VCE DPM. v2: update to the new API Reviewed-by:
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Alex Deucher authored
Used by the powerplay dpm code. v2: update to the new API v3: drop old include Reviewed-by:
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Alex Deucher authored
Used by the non-powerplay dpm code. v2: update to the new API Reviewed-by:
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Alex Deucher authored
Will be used by the new info ioctl query. v2: fetch a single state per request Reviewed-by:
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Alex Deucher authored
This is needed to set up the vce clock table in userspace for proper VCE DPM. v2: fix copy paste typo in comment v3: track number of valid states Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
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Alex Deucher authored
No intended functional change. Reviewed-by:
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Christian König authored
They are constant as well. v2: update uvd and vce phys ring structures as well Signed-off-by:
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Christian König authored
It's constant, so it doesn't make to much sense to keep it with the variable data. v2: update vce and uvd phys mode ring structures as well Signed-off-by:
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Christian König authored
I should have suggested that on the initial patchset. This saves us a few CPU cycles during CS and a bunch of loc. Signed-off-by:
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Christian König authored
sed -i "/\.parse_cs = NULL,/d" drivers/gpu/drm/amd/amdgpu/*.c That's just a leftover from radeon. Signed-off-by:
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Christian König authored
With the padding raised to 256 DW that shouldn't be needed any more. v2: reduce estimation as well Signed-off-by:
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Christian König authored
If a ring doesn't support that it shouldn't implement the function. Signed-off-by:
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Christian König authored
The same as on windows to avoid further problems with CE/DE command submission overlaps. Signed-off-by:
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Alex Deucher authored
Update the comment to explain why we do this. Reviewed-by:
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Alex Deucher authored
Update the comment to explain why we do this. Reviewed-by:
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Alex Deucher authored
Using the cached values has less latency for bare metal and SR-IOV, and prevents reading back bogus values if the engine is powergated. v2: fix typo in tile idx calculation Reviewed-by:
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Alex Deucher authored
Simplify the code and properly set the csb for harvest values. Reviewed-by:
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Alex Deucher authored
Needed when for SR-IOV and when PG is enabled. Reviewed-by:
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Alex Deucher authored
We need to cache some additional values to handle SR-IOV and PG. Reviewed-by:
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