- 21 Sep, 2010 40 commits
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Daniel Vetter authored
Like for the i915. Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk>
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Daniel Vetter authored
Beef up the generic version to support dmar. Otherwise like for the i830. v2: Don't try to DMA remap on resume for already remapped pages. Signed-off-by:
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Daniel Vetter authored
Well, not all too generic because it does not yet support dmar. Add a new function check_flags to ensure that non-gem code does not try to screw us over. v2: Beautify i830_check_flags with an idea from Chris Wilson. Signed-off-by:
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Daniel Vetter authored
Only used to remap the scratch page. Now that intel-gtt does this itself, kill the support code. Cc: Dave Airlie <airlied@linux.ie> Signed-off-by:
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Daniel Vetter authored
intel-gtt.c now handles the scratch page itself, so drop all that was just there to support it. Signed-off-by:
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Daniel Vetter authored
Like for i830. intel_i9xx_configure is now unused, so kill it. Signed-off-by:
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Daniel Vetter authored
Like for the i830. Signed-off-by:
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Daniel Vetter authored
And put it to use in the gtt configuration code that writes the scratch page addr in all gtt ptes. This makes intel_i830_configure generic, hence rename it to intel_fake_agp_configure. Signed-off-by:
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Daniel Vetter authored
The intel gtt fake agp driver is the only agp driver to use dma address remapping. So it makes sense to fold this code back into the only user (and thus reduce the reliance on the agp code). This patch does the first step by initializing (and remapping) the scratch page in a new function intel_gtt_setup_scratch_page. Unfortunately intel_gtt_cleanup had to move to avoid a forward declaration. The new scratch page is not yet used, though. v2: Refactor out scratch page teardown. Suggested by Chris Wilson on irc. This makes it clear what's going on and results in a nice symmetry between setup and teardown. Signed-off-by:
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Chris Wilson authored
Keep a list of pinned objects and display it via debugfs. Now all objects that exist in the GTT are always tracked on one of the active, flushing, inactive or pinned lists. Signed-off-by: -
Chris Wilson authored
If we have queued a page flip on the current fb and then request a mode change, wait until the page flip completes before performing the new request. Signed-off-by: -
Chris Wilson authored
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Chris Wilson authored
Track if the gpu requires the fence for the execution of a batch buffer and so only wait upon the retirement of the object's last rendering seqno if the fence is in use by the GPU. Signed-off-by: -
Chris Wilson authored
Signed-off-by: -
Daniel Vetter authored
Always PAGE_SIZE and only complicates the code. Signed-off-by:
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Daniel Vetter authored
The compiler happily does that for us. Signed-off-by:
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Daniel Vetter authored
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Daniel Vetter authored
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Daniel Vetter authored
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Daniel Vetter authored
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Daniel Vetter authored
Documentation explicitly mentions that the ring registers are designed to have the same offsets relative to a base registers. Use this to fight the code beaurocratic in intel_ringbuffer.c. No code changes in this patch, just the new definitions. Signed-off-by:
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Daniel Vetter authored
This looks like a copy-paste remnant from the i810. All the regs that are actually used are already defined somewhere else in i915_reg.h! Signed-off-by:
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Chris Wilson authored
Use the ring abstraction to hide the details of having choose the appropriate flushing method. Signed-off-by: -
Chris Wilson authored
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Xiang, Haihao authored
This ring buffer is used for video decoding/encoding on Sandybridge. Signed-off-by:
Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by:
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Chris Wilson authored
As noted by Zhenyu, we can now simply replace the existing advance hook by calling the new set_tail function pointer directly. Signed-off-by: -
Xiang, Haihao authored
This is prepared for video codec ring buffer on Sandybridge. It is needed to read/write more than one register to move the tail pointer of the video codec ring on Sandybridge. Signed-off-by:
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Xiang, Haihao authored
Introduce intel_init_render_ring_buffer(), intel_init_bsd_ring_buffer for ring initialization. Signed-off-by:
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Xiang, Haihao authored
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Chris Wilson authored
Previously we only tidied up the active bo lists for chipsets were we would attempt to reset the GPU. However, this action is necessary for the system to continue and reclaim the dead bo for all chipsets. Pointed out, in passing, by Owain Ainsworth. Signed-off-by: -
Chris Wilson authored
Clear the GPU read domain for the inactive objects on a reset so that they are correctly invalidated on reuse. Signed-off-by: -
Chris Wilson authored
Owain Ainsworth noticed that the reset code failed to clear the flushing list leaving the driver in an inconsistent state following a hung GPU. Signed-off-by: -
Chris Wilson authored
When flushing the GPU domains,we emit a flush on *both* rings, even though they share a unified cache. Only emit the flush on the currently active ring. Signed-off-by: -
Chris Wilson authored
Change the semantics to retire any buffer older than the current seqno rather than repeatedly calling calling the function to retire the buffer at the head of the list matching the request seqno. Whilst this should have no semantic impact on the implementation, Daniel was wondering if there was a bug where we might miss a retirement and so end up with a continually growing active list. Signed-off-by: -
Chris Wilson authored
Signed-off-by: -
Chris Wilson authored
On more recent chipsets, restoring the display is not as simple as writing a few registers, so force a full modeset of the current configuration in order to retrain the display link. Signed-off-by: -
Kenneth Graunke authored
Ironlake's graphics reset register has to be accessed via the MCHBAR, rather than via PCI config space, which requires some refactoring. Signed-off-by:
Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
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Kenneth Graunke authored
The graphics domains are listed as GRDOM in the documentation, and the GDRST PCI config register (0xc0) is only valid on I965 and GM45. Newer chips (like Sandy Bridge) have a different GDRST. Signed-off-by:
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Kenneth Graunke authored
Previously, it was only being set if passed GDRST_FULL - but the only caller passed GDRST_RENDER. So the hardware never actually reset. The comments also did not match the code. Instead, just set the reset bit regardless of what flags were passed. The GPU now resets correctly on my GM45. Signed-off-by:
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Chris Wilson authored
Avoid confusion between i965g meaning broadwater and the gen4+ chipset families. Signed-off-by:
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