1. 14 Jun, 2017 4 commits
  2. 12 Jun, 2017 9 commits
    • Tony Lindgren's avatar
      ARM: dts: omap4-droid4: Configure CPCAP battery driver · c3d28e53
      Tony Lindgren authored
      Configure CPCAP battery driver.
      
      Cc: devicetree@vger.kernel.org
      Cc: Marcel Partap <mpartap@gmx.net>
      Cc: Michael Scott <michael.scott@linaro.org>
      Reviewed-by: default avatarSebastian Reichel <sebastian.reichel@collabora.co.uk>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      c3d28e53
    • Subhajit Paul's avatar
      ARM: dts: dra7xx-clocks: Use DPLL_GPU for GPU clocks · fcd104b5
      Subhajit Paul authored
      The GPU has two functional clocks - GPU_CORE_GCLK and GPU_HYD_GCLK.
      Both of these are mux clocks and are derived from the DPLL_CORE
      H14 output clock CORE_GPU_CLK by default. These clocks can also be
      be derived from DPLL_PER or DPLL_GPU.
      
      The GPU DPLL provides the output clocks primarily for the GPU.
      Configuring the GPU for different OPP clock frequencies is easier
      to achieve when using the DPLL_GPU rather than the other two DPLLs
      due to:
      1. minimal affect on any other output clocks from these DPLLs
      2. may require an impossible post-divider values on existing DPLLs
         without affecting other clocks.
      
      So, switch the GPU functional clocks to be sourced from GPU DPLL by
      default. This is done using the DT standard properties "assigned-clocks"
      and "assigned-clock-parents". Newer u-boots (from 2017.01 onwards) reuse
      and can update these properties to choose an appropriate one-time fixed
      OPP configuration as all the required ABB/AVS setup is performed within
      the bootloader. Note that there is no DVFS supported for any of the
      non-MPU domains. The DPLL will automatically transition into a low-power
      stop mode when the associated output clocks are not utilized or gated
      automatically.
      
      This patch also sets the initial values for the DPLL_GPU outputs.
      These values are chosen based on the OPP_NOM values defined as per
      recommendation from design team. The DPLL locked frequency is kept
      at 1277 MHz, so that the value for the divider clock, dpll_gpu_m2_ck,
      can be set to 425.67 MHz for OPP_NOM.
      Signed-off-by: default avatarSubhajit Paul <subhajit_paul@ti.com>
      [s-anna@ti.com: revise patch description]
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Acked-by: default avatarTero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      fcd104b5
    • Suman Anna's avatar
      ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates · 32a04832
      Suman Anna authored
      The IVA DPLL in DRA7xx provides the output clocks for only the IVAHD
      subsystem in DRA7xx as compared to previous OMAP generations when it
      provided the clocks for both DSP and IVAHD subsystems. This DPLL is
      currently not configured by older bootloaders. Use the DT standard
      properties "assigned-clocks" and "assigned-clock-rates" to set the
      IVA DPLL clock rate and the rates for its derivative clocks at boot
      time to properly initialize/lock this DPLL and be independent of the
      bootloader version. Newer u-boots (from 2017.01 onwards) reuse and
      can update these properties to choose an appropriate one-time fixed
      OPP configuration. The DPLL will automatically transition into a
      low-power stop mode when the associated output clocks are not
      utilized or gated automatically.
      
      The reset value of the divider M2 (that supplies the IVA_GFLCK, the
      functional clock for the IVAHD subsystem) does not match a specific
      OPP. So, the derived output clock from this IVA DPLL has to be
      initialized as well to avoid initializing these divider outputs to an
      incorrect frequencies.
      
      The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data
      Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The
      clock rates are chosen based on these OPP_NOM values and defined as per
      a DRA7xx PLL spec document. The DPLL locked frequency is 2300 MHz, so
      the dpll_iva_ck clock rate used is half of this value. The value for the
      divider clock, dpll_iva_m2_ck, has to be set to 388.333334 MHz or more
      for the divider clk logic to compute the appropriate divider value for
      OPP_NOM.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Acked-by: default avatarTero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      32a04832
    • Suman Anna's avatar
      ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock rates · 268f6644
      Suman Anna authored
      The DSP DPLL is a new DPLL compared to previous OMAP generations and
      supplies the root clocks for the DSP processors, as well as a mux
      input source for EVE sub-system (on applicable SoCs). This DPLL is
      currently not configured by older bootloaders. Use the DT standard
      properties "assigned-clocks" and "assigned-clock-rates" to set the
      DSP DPLL clock rate and the rates for its derivative clocks at boot
      time to properly initialize/lock this DPLL and be independent of the
      bootloader version. Newer u-boots (from 2017.01 onwards) reuse and
      can update these properties to choose an appropriate one-time fixed
      OPP configuration. The DPLL will automatically transition into a
      low-power stop mode when the associated output clocks are not
      utilized or gated automatically.
      
      The DSP DPLL provides two output clocks, DSP_GFCLK and EVE_GCLK. The
      desired rate for DSP_GFCLK is 600 MHz (same as DSP DPLL CLKOUT frequency),
      and is currently auto set due to the desired M2 divider value being the
      same as reset value for the locked frequency of 600 MHz. The EVE_GCLK
      however is required to be 400 MHz, so set the dpll_dsp_m3x2_ck's rate
      explicitly so that the divider is set properly. The dpll_dsp_m2_ck rate
      is also set explicitly to not rely on any implicit matching divider reset
      values to the locked DPLL frequency.
      
      The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data
      Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The
      clock rates are chosen based on these OPP_NOM values and defined as per
      a DRA7xx PLL spec document. The DPLL locked frequency is 1200 MHz, so
      the dpll_dsp_ck clock rate used is half of this value.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Acked-by: default avatarTero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      268f6644
    • Suman Anna's avatar
      ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL · 39879c7d
      Suman Anna authored
      The IPU1 functional clock is actually the output of a mux clock,
      ipu1_gfclk_mux. The mux clock is sourced by default from the
      DPLL_ABE_X2_CLK, and this results in a rather odd clock frequency
      (361 MHz) for the IPU1 functional clock on platforms where ABE_DPLL
      is configured properly. Reconfigure the mux clock to be sourced from
      CORE_IPU_ISS_BOOST_CLK (dpll_core_h22x2_ck), so that both the IPU1
      and IPU2 are running from the same clock and clocked at the same
      nominal frequency of 425 MHz.
      
      This also ensures that IPU1 functional clock is always configured
      properly and becomes independent of the state of the ABE DPLL on
      all boards.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Acked-by: default avatarTero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      39879c7d
    • Suman Anna's avatar
      ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock rates · b58104f0
      Suman Anna authored
      The IVA DPLL is not an essential DPLL for the functionality of a
      bootloader and is usually not configured (e.g. older u-boots configure
      it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer
      than 2014.01 do not even have an option), and this results in incorrect
      operating frequencies when trying to use a DSP or IVAHD, whose root
      clocks are derived from this DPLL. Use the DT standard properties
      "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock
      rate and the rates for its derivative clocks at boot time to properly
      initialize/lock this DPLL. The DPLL will automatically transition
      into a low-power stop mode when the associated output clocks are
      not utilized or gated automatically.
      
      The reset values of the dividers H11 & H12 (functional clocks for DSP
      and IVAHD respectively) are identical to each other, but are different
      at each OPP. The reset values also do not match a specific OPP. So, the
      derived output clocks from the IVA DPLL have to be initialized as well
      to avoid initializing these divider outputs to incorrect frequencies.
      
      The clock rates are chosen based on the OPP_NOM values as defined in
      the OMAP5432 SR2.0 Data Manual Book vK, section 5.2.3.5 "DPLL_IVA
      Preferred Settings". The recommended maximum DPLL locked frequency is
      2330 MHz for OPP_NOM (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck
      clock rate used is half of this value. The value 465.92 MHz is used
      instead of 465.9 MHz for dpll_iva_h11x2_ck so that proper divider
      value can be calculated.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Acked-by: default avatarTero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      b58104f0
    • Suman Anna's avatar
      ARM: dts: omap44xx-clocks: Set IVA DPLL and its output clock rates · c8ceb5ac
      Suman Anna authored
      The IVA DPLL is not an essential DPLL for the functionality of a
      bootloader and is usually not configured (e.g. older u-boots configure
      it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer
      than 2014.01 do not even have an option), and this results in incorrect
      operating frequencies when trying to use a DSP or IVAHD, whose root
      clocks are derived from this DPLL. Use the DT standard properties
      "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock
      rate and the rates for its derivative clocks at boot time to properly
      initialize/lock this DPLL. The DPLL will automatically transition
      into a low-power stop mode when the associated output clocks are
      not utilized or gated automatically.
      
      The reset values of the dividers M4 & M5 (functional clocks for DSP and
      IVAHD respectively) are identical to each other, but are different at
      each OPP. The reset values also do not match a specific OPP. So, the
      derived output clocks from the IVA DPLL have to be initialized as well
      to avoid initializing these divider outputs to incorrect frequencies.
      
      The clock rates are chosen based on the OPP100 values as defined in the
      OMAP4430 ES2.x Public TRM vAP, section "3.6.3.8.7 DPLL_IVA Preferred
      Settings". The DPLL locked frequency is 1862.4 MHz (value for
      DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of
      this value.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Acked-by: default avatarTero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      c8ceb5ac
    • Sebastian Reichel's avatar
      ARM: dts: omap4-droid4: Fix WLAN compatible · d809f2cc
      Sebastian Reichel authored
      Motorola Droid 4 uses a WL1285C, so use proper compatible value.
      To avoid regressions while support for the new compatible value
      is added to the Linux kernel, the old compatible value is preserved
      as fallback.
      Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.co.uk>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      d809f2cc
    • Sebastian Reichel's avatar
      ARM: dts: omap4-droid4: Add isl29030 ALS/proximity sensor · 6f0b0c03
      Sebastian Reichel authored
      The Droid 4 has a isl29030 to measure ambient light (e.g. for
      automatically adapting display brightness) and proximity.
      Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.co.uk>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      6f0b0c03
  3. 06 Jun, 2017 5 commits
  4. 31 May, 2017 1 commit
  5. 26 May, 2017 8 commits
  6. 19 May, 2017 1 commit
  7. 16 May, 2017 5 commits
  8. 13 May, 2017 5 commits
    • Linus Torvalds's avatar
      Linux 4.12-rc1 · 2ea659a9
      Linus Torvalds authored
      2ea659a9
    • Linus Torvalds's avatar
      Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input · cd636458
      Linus Torvalds authored
      Pull some more input subsystem updates from Dmitry Torokhov:
       "An updated xpad driver with a few more recognized device IDs, and a
        new psxpad-spi driver, allowing connecting Playstation 1 and 2 joypads
        via SPI bus"
      
      * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input:
        Input: cros_ec_keyb - remove extraneous 'const'
        Input: add support for PlayStation 1/2 joypads connected via SPI
        Input: xpad - add USB IDs for Mad Catz Brawlstick and Razer Sabertooth
        Input: xpad - sync supported devices with xboxdrv
        Input: xpad - sort supported devices by USB ID
      cd636458
    • Linus Torvalds's avatar
      Merge tag 'upstream-4.12-rc1' of git://git.infradead.org/linux-ubifs · b53c4d5e
      Linus Torvalds authored
      Pull UBI/UBIFS updates from Richard Weinberger:
      
       - new config option CONFIG_UBIFS_FS_SECURITY
      
       - minor improvements
      
       - random fixes
      
      * tag 'upstream-4.12-rc1' of git://git.infradead.org/linux-ubifs:
        ubi: Add debugfs file for tracking PEB state
        ubifs: Fix a typo in comment of ioctl2ubifs & ubifs2ioctl
        ubifs: Remove unnecessary assignment
        ubifs: Fix cut and paste error on sb type comparisons
        ubi: fastmap: Fix slab corruption
        ubifs: Add CONFIG_UBIFS_FS_SECURITY to disable/enable security labels
        ubi: Make mtd parameter readable
        ubi: Fix section mismatch
      b53c4d5e
    • Linus Torvalds's avatar
      Merge branch 'for-linus-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml · ec059019
      Linus Torvalds authored
      Pull UML fixes from Richard Weinberger:
       "No new stuff, just fixes"
      
      * 'for-linus-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml:
        um: Add missing NR_CPUS include
        um: Fix to call read_initrd after init_bootmem
        um: Include kbuild.h instead of duplicating its macros
        um: Fix PTRACE_POKEUSER on x86_64
        um: Set number of CPUs
        um: Fix _print_addr()
      ec059019
    • Linus Torvalds's avatar
      Merge branch 'akpm' (patches from Andrew) · 1251704a
      Linus Torvalds authored
      Merge misc fixes from Andrew Morton:
       "15 fixes"
      
      * emailed patches from Andrew Morton <akpm@linux-foundation.org>:
        mm, docs: update memory.stat description with workingset* entries
        mm: vmscan: scan until it finds eligible pages
        mm, thp: copying user pages must schedule on collapse
        dax: fix PMD data corruption when fault races with write
        dax: fix data corruption when fault races with write
        ext4: return to starting transaction in ext4_dax_huge_fault()
        mm: fix data corruption due to stale mmap reads
        dax: prevent invalidation of mapped DAX entries
        Tigran has moved
        mm, vmalloc: fix vmalloc users tracking properly
        mm/khugepaged: add missed tracepoint for collapse_huge_page_swapin
        gcov: support GCC 7.1
        mm, vmstat: Remove spurious WARN() during zoneinfo print
        time: delete current_fs_time()
        hwpoison, memcg: forcibly uncharge LRU pages
      1251704a
  9. 12 May, 2017 2 commits
    • Roman Gushchin's avatar
      mm, docs: update memory.stat description with workingset* entries · b340959e
      Roman Gushchin authored
      Commit 4b4cea91691d ("mm: vmscan: fix IO/refault regression in cache
      workingset transition") introduced three new entries in memory stat
      file:
      
       - workingset_refault
       - workingset_activate
       - workingset_nodereclaim
      
      This commit adds a corresponding description to the cgroup v2 docs.
      
      Link: http://lkml.kernel.org/r/1494530293-31236-1-git-send-email-guro@fb.comSigned-off-by: default avatarRoman Gushchin <guro@fb.com>
      Cc: Johannes Weiner <hannes@cmpxchg.org>
      Cc: Michal Hocko <mhocko@kernel.org>
      Cc: Vladimir Davydov <vdavydov.dev@gmail.com>
      Cc: Tejun Heo <tj@kernel.org>
      Cc: Li Zefan <lizefan@huawei.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      b340959e
    • Minchan Kim's avatar
      mm: vmscan: scan until it finds eligible pages · 791b48b6
      Minchan Kim authored
      Although there are a ton of free swap and anonymous LRU page in elgible
      zones, OOM happened.
      
        balloon invoked oom-killer: gfp_mask=0x17080c0(GFP_KERNEL_ACCOUNT|__GFP_ZERO|__GFP_NOTRACK), nodemask=(null),  order=0, oom_score_adj=0
        CPU: 7 PID: 1138 Comm: balloon Not tainted 4.11.0-rc6-mm1-zram-00289-ge228d67e9677-dirty #17
        Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014
        Call Trace:
         oom_kill_process+0x21d/0x3f0
         out_of_memory+0xd8/0x390
         __alloc_pages_slowpath+0xbc1/0xc50
         __alloc_pages_nodemask+0x1a5/0x1c0
         pte_alloc_one+0x20/0x50
         __pte_alloc+0x1e/0x110
         __handle_mm_fault+0x919/0x960
         handle_mm_fault+0x77/0x120
         __do_page_fault+0x27a/0x550
         trace_do_page_fault+0x43/0x150
         do_async_page_fault+0x2c/0x90
         async_page_fault+0x28/0x30
        Mem-Info:
        active_anon:424716 inactive_anon:65314 isolated_anon:0
         active_file:52 inactive_file:46 isolated_file:0
         unevictable:0 dirty:27 writeback:0 unstable:0
         slab_reclaimable:3967 slab_unreclaimable:4125
         mapped:133 shmem:43 pagetables:1674 bounce:0
         free:4637 free_pcp:225 free_cma:0
        Node 0 active_anon:1698864kB inactive_anon:261256kB active_file:208kB inactive_file:184kB unevictable:0kB isolated(anon):0kB isolated(file):0kB mapped:532kB dirty:108kB writeback:0kB shmem:172kB writeback_tmp:0kB unstable:0kB all_unreclaimable? no
        DMA free:7316kB min:32kB low:44kB high:56kB active_anon:8064kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB writepending:0kB present:15992kB managed:15908kB mlocked:0kB slab_reclaimable:464kB slab_unreclaimable:40kB kernel_stack:0kB pagetables:24kB bounce:0kB free_pcp:0kB local_pcp:0kB free_cma:0kB
        lowmem_reserve[]: 0 992 992 1952
        DMA32 free:9088kB min:2048kB low:3064kB high:4080kB active_anon:952176kB inactive_anon:0kB active_file:36kB inactive_file:0kB unevictable:0kB writepending:88kB present:1032192kB managed:1019388kB mlocked:0kB slab_reclaimable:13532kB slab_unreclaimable:16460kB kernel_stack:3552kB pagetables:6672kB bounce:0kB free_pcp:56kB local_pcp:24kB free_cma:0kB
        lowmem_reserve[]: 0 0 0 959
        Movable free:3644kB min:1980kB low:2960kB high:3940kB active_anon:738560kB inactive_anon:261340kB active_file:188kB inactive_file:640kB unevictable:0kB writepending:20kB present:1048444kB managed:1010816kB mlocked:0kB slab_reclaimable:0kB slab_unreclaimable:0kB kernel_stack:0kB pagetables:0kB bounce:0kB free_pcp:832kB local_pcp:60kB free_cma:0kB
        lowmem_reserve[]: 0 0 0 0
        DMA: 1*4kB (E) 0*8kB 18*16kB (E) 10*32kB (E) 10*64kB (E) 9*128kB (ME) 8*256kB (E) 2*512kB (E) 2*1024kB (E) 0*2048kB 0*4096kB = 7524kB
        DMA32: 417*4kB (UMEH) 181*8kB (UMEH) 68*16kB (UMEH) 48*32kB (UMEH) 14*64kB (MH) 3*128kB (M) 1*256kB (H) 1*512kB (M) 2*1024kB (M) 0*2048kB 0*4096kB = 9836kB
        Movable: 1*4kB (M) 1*8kB (M) 1*16kB (M) 1*32kB (M) 0*64kB 1*128kB (M) 2*256kB (M) 4*512kB (M) 1*1024kB (M) 0*2048kB 0*4096kB = 3772kB
        378 total pagecache pages
        17 pages in swap cache
        Swap cache stats: add 17325, delete 17302, find 0/27
        Free swap  = 978940kB
        Total swap = 1048572kB
        524157 pages RAM
        0 pages HighMem/MovableOnly
        12629 pages reserved
        0 pages cma reserved
        0 pages hwpoisoned
        [ pid ]   uid  tgid total_vm      rss nr_ptes nr_pmds swapents oom_score_adj name
        [  433]     0   433     4904        5      14       3       82             0 upstart-udev-br
        [  438]     0   438    12371        5      27       3      191         -1000 systemd-udevd
      
      With investigation, skipping page of isolate_lru_pages makes reclaim
      void because it returns zero nr_taken easily so LRU shrinking is
      effectively nothing and just increases priority aggressively.  Finally,
      OOM happens.
      
      The problem is that get_scan_count determines nr_to_scan with eligible
      zones so although priority drops to zero, it couldn't reclaim any pages
      if the LRU contains mostly ineligible pages.
      
      get_scan_count:
      
              size = lruvec_lru_size(lruvec, lru, sc->reclaim_idx);
      	size = size >> sc->priority;
      
      Assumes sc->priority is 0 and LRU list is as follows.
      
      	N-N-N-N-H-H-H-H-H-H-H-H-H-H-H-H-H-H-H-H
      
      (Ie, small eligible pages are in the head of LRU but others are
       almost ineligible pages)
      
      In that case, size becomes 4 so VM want to scan 4 pages but 4 pages from
      tail of the LRU are not eligible pages.  If get_scan_count counts
      skipped pages, it doesn't reclaim any pages remained after scanning 4
      pages so it ends up OOM happening.
      
      This patch makes isolate_lru_pages try to scan pages until it encounters
      eligible zones's pages.
      
      [akpm@linux-foundation.org: clean up mind-bending `for' statement.  Tweak comment text]
      Fixes: 3db65812 ("Revert "mm, vmscan: account for skipped pages as a partial scan"")
      Link: http://lkml.kernel.org/r/1494457232-27401-1-git-send-email-minchan@kernel.orgSigned-off-by: default avatarMinchan Kim <minchan@kernel.org>
      Acked-by: default avatarMichal Hocko <mhocko@suse.com>
      Acked-by: default avatarJohannes Weiner <hannes@cmpxchg.org>
      Cc: Mel Gorman <mgorman@techsingularity.net>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      791b48b6