- 24 Nov, 2014 40 commits
-
-
John Crispin authored
We already have a read and write wrapper. This adds the missing mask wrapper. Signed-off-by:
John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8001/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
-
John Crispin authored
Signed-off-by:
-
John Crispin authored
Print the PMU and LDO settings on boot. Signed-off-by:
-
John Crispin authored
Signed-off-by:
Thomas Langer <thomas.langer@lantiq.com> Signed-off-by:
-
John Crispin authored
The code to detect unfused SoCs was broken due to missing register masking. Signed-off-by:
-
John Crispin authored
This is a regression caused by: commit afb46f79 Author: Rob Herring <robh@kernel.org> Date: Wed Apr 2 19:07:24 2014 -0500 mips: ralink: convert to use unflatten_and_copy_device_tree Make the of init code reuse the cmdline defined inside the dts. Signed-off-by:
-
John Crispin authored
The eiu init failed as the irq_domain was not yet available. Signed-off-by:
-
John Crispin authored
The voice and dsl drivers need to know which SoC we are running on. Signed-off-by:
Álvaro Fernández Rojas <noltari@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/8046/Signed-off-by:
-
John Crispin authored
VR9 needs different firmware files for the various phy/soc revisions. Some boards are ship with older and newer SoC revisions. To be able to boot a single image on all versions we need to define both firmware files inside the devicetree. Signed-off-by:
-
John Crispin authored
A reboot sometimes lead to a none working phy. An explicit reboot fixes the problem. Signed-off-by:
-
John Crispin authored
Add a reset-controller binding for the reset registers found on the lantiq SoC. Signed-off-by:
-
John Crispin authored
The Lantiq SoCs have a 2nd mips core called "voice mips macro core (vmmc)" which is used to run the voice firmware. This driver allows us to register a chunk of memory that the voice driver can later use for the 2nd core. Signed-off-by:
-
Tomeu Vizoso authored
Replacing it with a call to __clk_is_prepared(), which isn't entirely equivalent but in practice shouldn't matter. Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8120/Signed-off-by:
-
Andrew Bresticker authored
Bump up the rating of the GIC timer so that it gets prioritized over the CP0 timer. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8141/Signed-off-by:
-
Andrew Bresticker authored
Use clockevents_config_and_register to setup the clock_event_device based on frequency and min/max ticks instead of doing it ourselves. Signed-off-by:
-
Andrew Bresticker authored
Instead of requiring an explicit call to gic_clockevent_init in the SMP startup path, use CPU notifiers to register and enable the GIC timer on CPU startup. Signed-off-by:
-
Andrew Bresticker authored
Since the GIC timer IRQ is a percpu IRQ, we can use percpu_dev_id to pass the IRQ handler the correct clock_event_device. Signed-off-by:
-
Andrew Bresticker authored
Remove gic_event_handler since it is completely unnecessary. Signed-off-by:
-
Andrew Bresticker authored
There's no reason for gic_frequency to be global any more and it certainly doesn't belong in the GIC irqchip driver, so move it to the GIC clocksource driver. Signed-off-by:
-
Andrew Bresticker authored
There are a number of variables and functions which are unnecessarily global. Mark them static. Signed-off-by:
-
Andrew Bresticker authored
Combine the GIC clocksource driver with the GIC clockevent driver from arch/mips/kernel/cevt-gic.c and remove the clockevent driver's separate Kconfig symbol. Signed-off-by:
-
Andrew Bresticker authored
Move the GIC clocksource driver to drivers/clocksource/mips-gic-timer.c. Signed-off-by:
-
Andrew Bresticker authored
Use the GIC_SH_WEDGE_{SET,CLR} macros provided by mips-gic.h. Signed-off-by: -
Andrew Bresticker authored
There's no reason for the pending and masked interrupt bitmasks to be global. Just declare them on the stack in gic_get_int() since they only consume (256*2)/8 = 64 bytes. Signed-off-by:
-
Andrew Bresticker authored
Sort the #includes and remove those which are unnecessary. Signed-off-by:
-
Andrew Bresticker authored
Remove duplicate #defines and unnecessary #includes, fix parenthesization, and re-order register definitions in ascending order. Signed-off-by:
-
Kevin Cernekee authored
This hardware shows up on the newly-supported BCM3384 cable chip, as well as several old BCM63xx DSL chips. Signed-off-by:
Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8172/Signed-off-by:
-
Kevin Cernekee authored
Add myself as a maintainer for the new BCM3384 board support code. Signed-off-by:
-
Kevin Cernekee authored
This supports SMP Linux running on the BCM3384 Zephyr (BMIPS5000) application processor, with fully functional UART and USB 1.1/2.0. Device Tree is used to configure the following items: - All peripherals - Early console base address - SMP or UP mode - MIPS counter frequency - Memory size / regions - DMA offset - Kernel command line The DT-enabled bootloader and build instructions are posted at https://github.com/Broadcom/aeolusSigned-off-by:
-
Kevin Cernekee authored
We have a bunch of platforms using "mti,cpu-interrupt-controller" but the "mti" prefix isn't documented. Fix this. Signed-off-by:
-
Kevin Cernekee authored
This covers the new "brcm,*" devices added in the upcoming bcm3384 commit. Signed-off-by:
-
Kevin Cernekee authored
A couple of platforms register two buses and call of_platform_populate(). Move this into a common function to reduce duplication. Signed-off-by:
-
Kevin Cernekee authored
This is a dual core (quad thread) BMIPS5000. It needs a little extra code to boot the second core (CPU2/CPU3), but for now we can treat it the same as a single core BMIPS5000. Signed-off-by:
-
Kevin Cernekee authored
BMIPS435x and BMIPS438x have a single shared L1 D$ and load/store unit, so it isn't necessary to raise IPIs to keep both CPUs coherent. BMIPS5000 has VIPT L1 caches that handle aliases in hardware, and its I$ fills from D$. But a special sequence with 2 SYNCs and 32 NOPs is needed to ensure coherency. Signed-off-by:
-
Kevin Cernekee authored
On some chips like bcm3384, "other stuff" gets wired up to CPU1's IE_IRQ1 input, generating spurious IRQs. In this case we want the platform code to be able to mask it off. Signed-off-by:
-
Kevin Cernekee authored
BMIPS438x has a 64-byte D$ line size and BMIPS5000 has a 128-byte L2 line size. If L1_CACHE_SHIFT is undersized, DMA buffers will not be cacheline-aligned and terrible things will happen. Signed-off-by:
-
Kevin Cernekee authored
CONFIG_MIPS_CPU_SCACHE determines whether to build sc-mips.c. However, it is currently hardwired to use an L1_SHIFT of 6 (64 bytes). Move the L1_SHIFT selection into the CPU or SoC section so that other SoCs can select different values. Signed-off-by:
-
Kevin Cernekee authored
The secondary CPU's reset vector needs to be set to KSEG1 for a cold boot (release from reset), or KSEG0 for a warm restart. On a cold boot KSEG0 may be unavailable (BMIPS4380), and on a warm restart KSEG1 may be unavailable (XKS01 mode on 4380 or 5000). Signed-off-by:
-
Jon Fraser authored
CPU interrupts need to be disabled on a cpu being taken down. When a cpu is hot-plugged out of the system the following sequence occurs. On the CPU where the hotplug sequence was initiated: cpu_down _cpu_down { __cpu_notify(CPU_DOWN_PREPARE __stop_machine(take_cpu_down wait for cpu to run disable code. __cpu_die } On the CPU being disabled: take_cpu_down __cpu_disable { mp_ops->cpu_disable bmips_cpu_disable clear_c0_status(IE_IRQ5) (added) cpu_notify(CPU_DYING... } Before the cpu_notifier is called with CPU_DYING, all interrupts on the dying cpu must be disabled. This guarantees that before tick_notify is called with the CPU_DYING event and sets the clock device pointer to NULL, there can not be any more clock interrupts. When this wasn't done, an unfortunately-timed timer interrupt sometimes caused hangs immediately prior to system suspend: Debug PM is not enabled. To enable partial suspend, rebuild kernel with CONFIG_PM_DEBUG Pass 1 out of 1,PM: Syncing filesystems ... mode=none, tp1=done. 1, flags=5, cycle_tp=, sleep= Freezing user space processes ... (elapsed 0.01 seconds) done. Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done. PM: suspend of devices complete after 54.199 msecs PM: late suspend of devices complete after 0.172 msecs Disabling non-boot CPUs ... SMP: CPU1 is offline INFO: rcu_sched detected stalls on CPUs/tasks: { 3} (detected by 0, t=62537 jiffies) Call Trace: [<804baa78>] dump_stack+0x8/0x34 [<8008a2d8>] __rcu_pending+0x4b8/0x55c [<8008adf4>] rcu_check_callbacks+0x78/0x180 [<80037830>] update_process_times+0x40/0x6c [<80072fe4>] tick_sched_timer+0x74/0xe4 [<80050180>] __run_hrtimer.clone.30+0x64/0x140 [<80051150>] hrtimer_interrupt+0x19c/0x4bc [<8000cdb8>] c0_compare_interrupt+0x50/0x88 [<80081b18>] handle_irq_event_percpu+0x5c/0x2f4 [<80086490>] handle_percpu_irq+0x8c/0xc0 [<800811b4>] generic_handle_irq+0x34/0x54 [<800067dc>] do_IRQ+0x18/0x2c [<8000375c>] plat_irq_dispatch+0xd0/0x128 [<80004a04>] ret_from_irq+0x0/0x4 [<80004c40>] r4k_wait+0x20/0x40 [<80006b6c>] cpu_idle+0x98/0xf0 [<805d3988>] start_kernel+0x424/0x440 Signed-off-by:Jon Fraser <jfraser@broadcom.com> Signed-off-by:
-
Jon Fraser authored
BMIPS3300 processors do not have the hardware to support SMP, but with a small tweak, the SMP ebase relocation code allows BMIPS3300-based platforms to reuse the S2/S3 power management code from BMIPS4380-based chips. Normally this is as simple as adding one line to prom_init(): board_ebase_setup = &bmips_ebase_setup; Signed-off-by:
-
