- 21 Apr, 2023 5 commits
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Srinivasan Shanmugam authored
Fix following checkpatch style errors in amdgpu_drv.c & amdgpu_device.c ERROR: exactly one space required after that #ifdef ERROR: spaces required around that '+=' (ctx:WxV) ERROR: space required before the open brace '{' ERROR: spaces required around that '||' (ctx:VxE) ERROR: space prohibited before that close parenthesis ')' ERROR: space required before the open parenthesis '(' ERROR: space required before the open brace '{' ERROR: code indent should use tabs where possible Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Srinivasan Shanmugam authored
Fix the following errors reported by checkpatch: ERROR: space prohibited before open square bracket '[' +#define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type ERROR: code indent should use tabs where possible + query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;$ Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Candice Li authored
Some ASICs support fatal error event but do not support pcie_bif ras. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Longlong Yao authored
The following call trace is observed when removing the amdgpu driver, which is caused by that BOs allocated for psp are not freed until removing. [61811.450562] RIP: 0010:amddrm_buddy_fini.cold+0x29/0x47 [amddrm_buddy] [61811.450577] Call Trace: [61811.450577] <TASK> [61811.450579] amdgpu_vram_mgr_fini+0x135/0x1c0 [amdgpu] [61811.450728] amdgpu_ttm_fini+0x207/0x290 [amdgpu] [61811.450870] amdgpu_bo_fini+0x27/0xa0 [amdgpu] [61811.451012] gmc_v9_0_sw_fini+0x4a/0x60 [amdgpu] [61811.451166] amdgpu_device_fini_sw+0x117/0x520 [amdgpu] [61811.451306] amdgpu_driver_release_kms+0x16/0x30 [amdgpu] [61811.451447] devm_drm_dev_init_release+0x4d/0x80 [drm] [61811.451466] devm_action_release+0x15/0x20 [61811.451469] release_nodes+0x40/0xb0 [61811.451471] devres_release_all+0x9b/0xd0 [61811.451473] __device_release_driver+0x1bb/0x2a0 [61811.451476] driver_detach+0xf3/0x140 [61811.451479] bus_remove_driver+0x6c/0xf0 [61811.451481] driver_unregister+0x31/0x60 [61811.451483] pci_unregister_driver+0x40/0x90 [61811.451486] amdgpu_exit+0x15/0x447 [amdgpu] For smu v13_0_2, if the GPU supports xgmi, refer to commit f5c7e779 ("drm/amdgpu: Adjust removal control flow for smu v13_0_2"), it will run gpu recover in AMDGPU_RESET_FOR_DEVICE_REMOVE mode when removing, which makes all devices in hive list have hw reset but no resume except the basic ip blocks, then other ip blocks will not call .hw_fini according to ip_block.status.hw. Since psp_free_shared_bufs just includes some software operations, so move it to psp_sw_fini. Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
Longlong Yao <Longlong.Yao@amd.com> Signed-off-by:
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Cruise Hung authored
[Why & How] We missed resetting OUTBOX0 mailbox r/w pointer on DMUB reset. Fix it. Fixes: 6ecf9773 ("drm/amd/display: Fix DMUB outbox trace in S4 (#4465)") Signed-off-by:
Cruise Hung <Cruise.Hung@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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- 20 Apr, 2023 4 commits
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Le Ma authored
Assign value here as the num_xcd is referenced in some gfx9 common path. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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Le Ma authored
Skip KCQ setup on slave xcc as there's no use case. Signed-off-by:
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Samson Tam authored
[Why] Workaround for DMCUB front door load [How] Clear GPINT after reset so its consistent Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why&How] Fix CLK MGR early initialization and add logging. Fixes: 265280b9 ("drm/amd/display: add CLKMGR changes for DCN32/321") Reviewed-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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- 18 Apr, 2023 31 commits
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Le Ma authored
v1: To support multple XCD case (Le) v2: unify naming style (Le) v3: apply the changes to gc v11_0 (Hawking) v4: apply the changes to gc SOC21 (Morris) Signed-off-by:
Morris Zhang <Shiwu.Zhang@amd.com> Signed-off-by:
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Le Ma authored
v1: To support multiple XCD case (Le) v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking) Signed-off-by:
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Le Ma authored
Change those v9_4_3 interfaces which are exposed in gfx_v9_0.c. For some active single-xcc emu models, the code path in gfx_v9_0.c is better to keep reserved for a while. Signed-off-by:
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Le Ma authored
Each XCD needs to be initialized respectively. The major changes are: 1. add iteration to do rlc/kiq/kcq init/fini for each xcd 2. load rlc/mec microcode to each xcd 3. add argument to specify xcc index in initialization functions Signed-off-by:
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Le Ma authored
To support grbm select for multiple XCD case. v2: unify naming style Signed-off-by:
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Le Ma authored
To prepare for gc v9_4_3 specific feature. v2: fix exports (Alex) Signed-off-by:
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Le Ma authored
v1: Modify kiq_init/fini, mqd_sw_init/fini and enable/disable_kcq to adapt to multi-die case. Pass 0 as default to all asics with single xcc (Le) v2: squash commits to avoid breaking the build (Le) v3: unify naming style (Le) v4: apply the changes to gc v11_0 (Hawking) Signed-off-by:
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Le Ma authored
This will benifit the mqd indexing for kiq/kcq in multi XCD case. Signed-off-by:
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Le Ma authored
To allocate independent queue_bitmap for each XCD, then the old bitmap policy can be continued to use with a clear logic. Use mec_bitmap[0] as default for all non-GC 9.4.3 IPs. v2: squash commits to avoid breaking the build v3: unify naming style Signed-off-by:
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Le Ma authored
v1: more kiq instances are a available in SOC (Le) v2: squash commits to avoid breaking the build (Le) v3: make the conversion for gfx/mec v11_0 (Hawking) Signed-off-by:
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Nikita Zhandarovich authored
Several calls to ci_dpm_fini() will attempt to free resources that either have been freed before or haven't been allocated yet. This may lead to undefined or dangerous behaviour. For instance, if r600_parse_extended_power_table() fails, it might call r600_free_extended_power_table() as will ci_dpm_fini() later during error handling. Fix this by only freeing pointers to objects previously allocated. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: cc8dbbb4 ("drm/radeon: add dpm support for CI dGPUs (v2)") Co-developed-by:
Natalia Petrova <n.petrova@fintech.ru> Signed-off-by:
Nikita Zhandarovich <n.zhandarovich@fintech.ru> Signed-off-by:
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Tom Rix authored
cpp_check reports drivers/gpu/drm/amd/display/modules/freesync/freesync.c:1143:17: style: Variable 'oldest_index' is assigned a value that is never used. [unreadVariable] oldest_index = 0; ^ This variable is not used so remove. Signed-off-by:Tom Rix <trix@redhat.com> Signed-off-by:
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Alan Liu authored
[Why] After gpu-reset, sometimes the driver fails to enable vblank irq, causing flip_done timed out and the desktop freezed. During gpu-reset, we disable and enable vblank irq in dm_suspend() and dm_resume(). Later on in amdgpu_irq_gpu_reset_resume_helper(), we check irqs' refcount and decide to enable or disable the irqs again. However, we have 2 sets of API for controling vblank irq, one is dm_vblank_get/put() and another is amdgpu_irq_get/put(). Each API has its own refcount and flag to store the state of vblank irq, and they are not synchronized. In drm we use the first API to control vblank irq but in amdgpu_irq_gpu_reset_resume_helper() we use the second set of API. The failure happens when vblank irq was enabled by dm_vblank_get() before gpu-reset, we have vblank->enabled true. However, during gpu-reset, in amdgpu_irq_gpu_reset_resume_helper() vblank irq's state checked from amdgpu_irq_update() is DISABLED. So finally it disables vblank irq again. After gpu-reset, if there is a cursor plane commit, the driver will try to enable vblank irq by calling drm_vblank_enable(), but the vblank->enabled is still true, so it fails to turn on vblank irq and causes flip_done can't be completed in vblank irq handler and desktop become freezed. [How] Combining the 2 vblank control APIs by letting drm's API finally calls amdgpu_irq's API, so the irq's refcount and state of both APIs can be synchronized. Also add a check to prevent refcount from being less then 0 in amdgpu_irq_put(). v2: - Add warning in amdgpu_irq_enable() if the irq is already disabled. - Call dc_interrupt_set() in dm_set_vblank() to avoid refcount change if it is in gpu-reset. v3: - Improve commit message and code comments. Signed-off-by:
Alan Liu <HaoPing.Liu@amd.com> Reviewed-by:
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Colin Ian King authored
There is a spelling mistake in the smu_i2c_bus_access prototype. Fix it. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
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Bas Nieuwenhuizen authored
This info would be used by radv to figure out when we need to split a submission into multiple submissions. radv currently has a limit of 192 which seems to work for most gfx submissions, but is way too high for e.g. compute or sdma. Userspace is available at https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3 v3: Completely rewrote based on suggestion of making it a separate query. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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Bas Nieuwenhuizen authored
And ensure each ring supports that many submissions. This makes sure that we don't get surprises after the submission has been scheduled where the ring allocation actually gets rejected. My calculations on the existing limits: COMPUTE v10: 128 COMPUTE v11: 128 COMPUTE v6: 157 COMPUTE v7: 133 COMPUTE v8: 130 COMPUTE v9: 125 GFX v10: 208 GFX v11: 213 GFX v6: 154 (doubling this in the previous patch) GFX v7: 226 GFX v8: 213 GFX v9: 208 GFX v9 (SW): 208 SDMA CIK: 87 SDMA SI: 97 SDMA v2.4: 74 SDMA v3.0: 74 SDMA v4.0: 72 SDMA v5.0: 51 SDMA v6.0: 52 UVD ENC v6.0: 98 UVD ENC v7.0: 92 UVD v3.1: 124 UVD v4.2: 124 UVD v5.0: 83 UVD v6.0 (VM): 55 UVD v7.0: 51 VCE v2.0: 126 VCE v3.0 (VM): 98 VCE v4.0: 93 VCN DEC v1.0: 49 VCN DEC v2.0: 51 VCN DEC v3.0: 51 VCN ENC v1.0: 58 VCN ENC v2.0: 93 VCN ENC v3.0: 93 VCN ENC v4.0: 93 VCN JPEG v1.0: 17 VCN JPEG v2.0: 16 VCN JPEG v2.5: 17 VCN JPEG v3.0: 17 VCN JPEG v4.0: 17 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498Reviewed-by:
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Bas Nieuwenhuizen authored
To ensure it supports 192 IBs per submission, so we can keep a simplified IB limit in the follow up patch without having to look at IP or GPU version. Reviewed-by:
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Alvin Lee authored
[Why&How] - Implement interface to program DTBCLK DTO’s according to reference DTBCLK returned by PMFW - This is required because DTO programming requires exact DTBCLK reference freq or it could result in underflow Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Arnd Bergmann authored
Three functions in the amdgpu display driver cause -Wmissing-prototype warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c:1858:6: error: no previous prototype for 'is_timing_changed' [-Werror=missing-prototypes] is_timing_changed() is actually meant to be a global symbol, but needs a proper name and prototype. Fixes: 17ce8a69 ("drm/amd/display: Add dsc pre-validation in atomic check") Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Wesley Chalmers authored
[WHY] Add log entry for when display refresh from MALL settings are sent to SMU. Fixes: 1664641e ("drm/amd/display: Add logger for SMU msg") Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Tianci Yin authored
[why] Since the variable fpu_recursion_depth is per-CPU type, it has one copy on each CPU, thread migration causes data consistency issue, then the call trace shows up. And preemption disabling can't prevent migration. [how] Disable migration to ensure consistency of fpu_recursion_depth. Reviewed-by:
Tianci Yin <tianci.yin@amd.com> Tested-by:
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Mikita Lipski authored
Extract edid's checksum and send it back for verification if EDID_TEST is requested. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why&How] Remove incorrect early return in a device specific fifo reset workaround Reviewed-by:
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Hersen Wu authored
[Why&How] We were not returning -EINVAL on DSC atomic check fail. Add it. Fixes: 71be4b16 ("drm/amd/display: dsc validate fail not pass to atomic check") Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Tested-by:
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Eric Yang authored
[Why] If optimized init is done in FW. DCN init can be skipped in driver. This need to be communicated between driver and fw and maintain backwards compatibility. [How] Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow so FW will perform it. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
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Dmytro Laktyushkin authored
[Why & How] Fix a typo for dcn315 line buffer bpp. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by:
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Daniel Miess authored
[Why] 1. It could hit bandwidth limitdation under single dimm memory when connecting 8K external monitor. 2. IsSupportedVidPn got validation failed with 2K240Hz eDP + 8K24Hz external monitor. 3. It's better to filter out such combination in EnumVidPnCofuncModality 4. For short term, filter out in dc bandwidth validation. [How] Force 2K@240Hz+8K@24Hz timing validation false in dc. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Daniel Miess <Daniel.Miess@amd.com> Tested-by:
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Jingwen Zhu authored
[Why] The eDP retrain will cause the DPCD 300 to be reset to default. And cause the brightness can't be set correctly. [How] delete the call to edp panel power control in both enable_link_output/disable_link_output entirely and only call edp panel control in enable_link_dp and disable_link_dp once. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Jingwen Zhu <Jingwen.Zhu@amd.com> Tested-by:
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Michael Mityushkin authored
[Why] When link training during engine recovery, ASSR might fail causing panel mode to be reset to default. This should not happen for eDP as it will prevent the panel from turning back on. [How] Added dp_panel_mode to struct dc_link to remember previously applied panel mode. Do not reset panel mode to default while performing link training if previously used panel mode = eDP. Reviewed-by:
Michael Mityushkin <michael.mityushkin@amd.com> Tested-by:
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Dmytro Laktyushkin authored
[Why & How] Add options for dc odm debug. Reviewed-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Alex Hung authored
[Why & How] timing.dsc_cfg.num_slices_v can be zero and it is necessary to check before using it. This fixes the error "divide error: 0000 [#1] PREEMPT SMP NOPTI". Reviewed-by:
Alex Hung <alex.hung@amd.com> Tested-by:
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