- 01 Oct, 2018 2 commits
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Christoph Manszewski authored
The mixer hardware supports both premultiplied alpha and non-premultiplied alpha. Currently premultiplied alpha is default, make this configurable. Tested on Odroid-U3 with Exynos 4412 CPU, kernel next-20180913 using modetest. Signed-off-by:
Christoph Manszewski <c.manszewski@samsung.com> Signed-off-by:
Inki Dae <inki.dae@samsung.com>
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Christoph Manszewski authored
Make use of helper functions in exynos_drm_plane_reset in order to set all default values. Currently alpha isn't set during reset. Signed-off-by:
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- 30 Sep, 2018 2 commits
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Marek Szyprowski authored
Add support for 16x16 tiled NV12 and NV21 formats. Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by:
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Andrzej Pietrasiewicz authored
Add support for 16x16 tiled formats: NV12/NV21, YUYV and YUV420. Signed-off-by:
Andrzej Pietrasiewicz <andrzej.p@samsung.com> Signed-off-by:
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- 20 Sep, 2018 8 commits
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Andrzej Pietrasiewicz authored
Add modifier for tiled formats used by graphics modules found in Samsung Exynos5250/542x/5433 SoCs. This is a simple tiled layout using tiles of 16x16 pixels in a row-major layout. Signed-off-by:
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Souptick Joarder authored
convert drm_atomic_helper_suspend/resume() to use drm_mode_config_helper_suspend/resume(). exynos_drm_fbdev_suspend/resume can be removed as drm_mode_config_helper_suspend/resume has implement the same in generic way. Remove suspend_state from exynos_drm_private struct as it is no more useful. Signed-off-by:
Ajit Negi <ajitn.linux@gmail.com> Signed-off-by:
Souptick Joarder <jrdr.linux@gmail.com> Tested-by:
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Andrzej Hajda authored
Of-graph bindings should describe ports present in the device, not the devices it can be connected to. The patch replaces verbose description with shorter but more precise one. While at it clock related properties are moved to the main node as it is their actual location. Signed-off-by:
Andrzej Hajda <a.hajda@samsung.com> Signed-off-by:
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Maciej Purski authored
As the out bridge will not be enabled directly by the framework, it should be enabled by DSI. exynos_dsi_enable() should handle a case, when there is an out_bridge connected as a DSI peripheral. Changed in v5: - fixed error path in exynos_dsi_enable Signed-off-by:
Maciej Purski <m.purski@samsung.com> [ a.hajda@samsung.com: v5 ] Signed-off-by:
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Maciej Purski authored
The current implementation assumes that the only possible peripheral device for DSIM is a panel. Using an output bridge child device should also be possible. If an output bridge is available, don't create a new connector. Instead, call drm_bridge_attach() and set encoder's bridge to NULL in order to avoid an out bridge from being visible by the framework, as the DSI bus needs control on enabling its child output bridge. Such sequence is required by Toshiba TC358764 bridge, which is a DSI peripheral bridge device. changed in v5: - detach bridge in mipi_dsi detach callback Signed-off-by:
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Maciej Purski authored
Driver uses bridge_node to refer to bridge on input side of DSI. Since we want to add support for bridges on output side lets add "in" prefix to avoid confusion with out bridges. Changes in v5: - replace mic_ prefix with in_ Signed-off-by:
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git://linuxtv.org/pinchartl/mediaDave Airlie authored
R-Car DU changes for v4.20 The pull request mostly contains updates to the R-Car DU driver, notably support for interlaced modes on Gen3 hardware, support for the LVDS output on R8A77980, and a set of miscellaneous bug fixes. There are also two SPDX conversion patches for the drm shmobile and panel-lvds drivers, as well as an update to MAINTAINERS to add Kieran Bingham as a co-maintainer for the DU driver. Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/3273568.LdoAI77IYW@avalon
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 4.20: UAPI Changes: - None Cross-subsystem Changes: - None Core Changes: - Allow drivers to disable features with per-device granularity (Ville) - Use EOPNOTSUPP when iface/feature is unsupported instead of EINVAL/errno soup (Chris) - Simplify M/N DP quirk by using constant N to limit size of M/N (Shawn) - add quirk for LG LP140WF6-SPM1 eDP panel (Shawn) Driver Changes: - i915/amdgpu: Disable DRIVER_ATOMIC for older/unsupported devices (Ville) - sun4i: add support for R40 HDMI PHY (Icenowy) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Icenowy Zheng <icenowy@aosc.io> Cc: Lee, Shawn C <shawn.c.lee@intel.com> Signed-off-by:
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- 19 Sep, 2018 6 commits
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Lee, Shawn C authored
The N value was computed by kernel driver that based on synchronous clock mode. But only specific N value (0x8000) would be acceptable for LG LP140WF6-SPM1 eDP panel which is running at asynchronous clock mode. With the other N value, Tcon will enter BITS mode and display black screen. Add this panel into quirk database and give particular N value when calculate M/N divider. v2: no update v3: add lost commit messages back for version 2 v4: send patch to both intel-gfx and dri-devel Cc: Jani Nikula <jani.nikula@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by:
Lee, Shawn C <shawn.c.lee@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1536733371-25004-4-git-send-email-shawn.c.lee@intel.com
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Lee, Shawn C authored
Some DP dongles in particular seem to be fussy about too large link M/N values. Set specific value for N divider can resolve this issue per dongle vendor's comment. So configure N as constant value (0x8000) to instead of reduce M/N formula when specific DP dongle connected. v2: add more comments for issue description and fix typo. v3: add lost commit messages back for version 2 v4: send patch to both intel-gfx and dri-devel Cc: Jani Nikula <jani.nikula@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> Tested-by:
Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by:
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Lee, Shawn C authored
DP quirk list just compare sink or branch device's OUI so far. That means particular vendor's products will be applied specific change. This change would confirm device_id the same or not. Then driver can implement some changes for branch/sink device that really need additional WA. v2: use sizeof instead of hard coded '6' v3: add lost commit messages back for version 2 v4: send patch to both intel-gfx and dri-devel Cc: Jani Nikula <jani.nikula@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> Tested-by:
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Jiandi An authored
With virtio gpu ttm-pages being dma mapped, dma sync is needed when swiotlb is used as bounce buffers, before TRANSFER_TO_HOST_2D/3D commands are sent. Signed-off-by:
Jiandi An <jiandi.an@amd.com> Link: http://patchwork.freedesktop.org/patch/msgid/20180919070931.91168-1-jiandi.an@amd.comSigned-off-by:
Gerd Hoffmann <kraxel@redhat.com>
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Icenowy Zheng authored
The R40 SoC has a HDMI PHY that is possible to mux two video PLLs. Add support for it. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180916043409.62374-4-icenowy@aosc.io
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Icenowy Zheng authored
The Allwinner R40 HDMI PHY is currently the only one that seems to be able to select between two PLL inputs. Add a compatible string for it, and the pll-1 clock input definition. Signed-off-by:
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- 15 Sep, 2018 9 commits
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Kieran Bingham authored
The Gen3 VSP used by the DU for display does not support the packed VYUY pixel format. Gen2 VSP hardware is able to process this format, but DU + VSP operation isn't enabled on Gen2, and VYUY isn't a strategic format, so it can be ignored. Remove the format from the capabilities of the DU driver. Signed-off-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Laurent Pinchart authored
The framebuffer pitch and alignment constraints reflect the limitations of the Gen2 DU hardware. On Gen3, the DU has no memory interface and thus doesn't impose any constraint. The limitations come instead from the VSP that has a limit of 65535 bytes for the pitch and no alignment constraint. Update the checks accordingly. Signed-off-by:
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Koji Matsuoka authored
This patch supports pixel format of RGB332, ARGB4444, XRGB4444, BGR888, RGB888, BGRA8888, BGRX8888 and YVYU. VYUY pixel format is not supported by H/W specification. Signed-off-by:
Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by:
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Kieran Bingham authored
The R-Car Gen3 DU utilises the VSP1 hardware for memory access. The limits on the RPF and WPF in this pipeline are 8190x8190. Update the supported maximum sizes accordingly. Signed-off-by:
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Sergei Shtylyov authored
Add support for the R-Car V3H (R8A77980) SoC to the LVDS encoder driver. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by:
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Jacopo Mondi authored
The ESCR and OTAR registers exist in each DU channel, but at different offsets for odd and even channels. This led to usage of the group register access API to write them, with offsets macros named ESCR/OTAR and ESCR2/OTAR2 for the first and second ESCR/OTAR register in the group respectively. The names are confusing as it suggests that the ESCR/OTAR registers for DU0 and DU2 are taken into account, especially with writes performed to the group register access API. Rename the offsets to ESCR/OTAR02 and ESCR/OTAR13, and use the CRTC register access API to clarify the code. The offsets values are updated accordingly. Cosmetic patch, no functional changes intended. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by:
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Jacopo Mondi authored
Document and re-name the 'dpll_ch' field to a more precise 'dpll_mask' for consistency with the 'channels_mask' field defined in 'struct rcar_du_device_info'. Signed-off-by:
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Jacopo Mondi authored
DU channels not equipped with a DPLL use an SoC internal (provided by the CPG) or external clock source combined with a DU internal divider to generate the desired output dot clock frequency. The current clock selection procedure does not fully exploit the ability of external clock sources to generate the exact dot clock frequency by themselves, but relies instead on tuning the internal DU clock divider only, resulting in a less precise clock generation process. When possible, and desirable, ask the external clock source for the exact output dot clock frequency, and select the clock source that produces the frequency closest to the desired output dot clock. This patch specifically targets platforms (like Salvator-X[S] and ULCBs) where the DU's input dotclock.in is generated by the versaclock VC5 clock source, which is capable of generating the exact rate the DU needs as pixel clock output. This patch fixes higher resolution modes which requires an high pixel clock output currently not working on non-HDMI DU channel (such as 1920x1080@60Hz on the VGA output). Fixes: 1b30dbde ("drm: rcar-du: Add support for external pixel clock") Signed-off-by:
Jacopo Mondi <jacopo@jmondi.org> [Factor out code to a helper function] Signed-off-by:
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Laurent Pinchart authored
The DU channels that have a display PLL (DPLL) can only use external clock sources, and don't have an internal clock divider (with the exception of H3 ES1.x where the post-divider is present and needs to be used as a workaround for a DPLL silicon issue). Rework the clock configuration to take this into account, avoiding selection of non-existing clock sources or usage of a missing post-divider. Signed-off-by:
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- 14 Sep, 2018 12 commits
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Chris Wilson authored
If the ioctl is not supported on a particular piece of HW/driver combination, report ENOTSUP (aka EOPNOTSUPP) so that it can be easily distinguished from both the lack of the ioctl and from a regular invalid parameter. v2: Across all the kms ioctls we had a mixture of reporting EINVAL, ENODEV and a few ENOTSUPP (most where EINVAL) for a failed drm_core_check_feature(). Update everybody to report ENOTSUPP. v3: ENOTSUPP is an internal errno! It's value (524) does not correspond to a POSIX errno, the one we want is ENOTSUP. However, uapi/asm-generic/errno.h doesn't include ENOTSUP but man errno says "ENOTSUP and EOPNOTSUPP have the same value on Linux, but according to POSIX.1 these error values should be distinct." so use EOPNOTSUPP as its equivalent. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20180913192050.24812-1-chris@chris-wilson.co.uk
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Kieran Bingham authored
Upcoming implementations of the R-Car DU have removed support for interlaced display pipelines. Provide a means to determine this based on the feature flags of the hardware configuration structs. Signed-off-by:
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Kieran Bingham authored
These flags are represented by bit fields. To make this clear, utilise the BIT() macro. Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
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Kieran Bingham authored
Use the newly exposed VSP1 interface to enable interlaced frame support through the VSP1 LIF pipelines. The DSMR register is updated to set the ODEV flag on interlaced pipelines, thus defining an interlaced stream as having the ODD field located in the second half (BOTTOM) of the frame buffer. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Kuninori Morimoto authored
Kconfig doesn't have license line, thus, it is GPL-2.0 as default. rcar_du_regs.h, rcar_lvds_regs.h are GPL-2.0, and all other files are GPL-2.0+ as original license. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by:
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Kuninori Morimoto authored
Signed-off-by:
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Kuninori Morimoto authored
Signed-off-by:
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Sergei Shtylyov authored
Document the R-Car V3H (R8A77980) SoC in the R-Car LVDS bindings. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Sergei Shtylyov authored
Document the R-Car V3H (R8A77980) SoC in the R-Car DU bindings; the DU hardware has the same topology as in the R-Car V3M (R8A77970). Signed-off-by:
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Kieran Bingham authored
Add myself as a co-maintainer for the Renesas DRM drivers. Signed-off-by:
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Dan Carpenter authored
We accidentally forgot to set "ret" on this error path so it means we return NULL instead of an error pointer. The caller checks for NULL and changes it to an error pointer so it doesn't cause an issue at run time. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Link: http://patchwork.freedesktop.org/patch/msgid/20180914065615.GA12043@mwandaSigned-off-by:
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Laurent Pinchart authored
The fbdev git tree referenced in the MAINTAINERS file doesn't exist anymore. Update the location to point to the new git tree. Signed-off-by:
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- 13 Sep, 2018 1 commit
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 4.20: UAPI Changes: - Add host endian variants for the most common formats (Gerd) - Fail ADDFB2 for big-endian drivers that don't advertise BE quirk (Gerd) - clear smem_start in fbdev for drm drivers to avoid leaking fb addr (Daniel) Cross-subsystem Changes: Core Changes: - fix drm_mode_addfb() on big endian machines (Gerd) - add timeline point to syncobj find+replace (Chunming) - more drmP.h removal effort (Daniel) - split uapi portions of drm_atomic.c into drm_atomic_uapi.c (Daniel) Driver Changes: - bochs: Convert open-coded portions to use helpers (Peter) - vkms: Add cursor support (Haneen) - udmabuf: Lots of fixups (mostly cosmetic afaict) (Gerd) - qxl: Convert to use fbdev helper (Peter) Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Chunming Zhou <david1.zhou@amd.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Peter Wu <peter@lekensteyn.nl> Cc: Haneen Mohammed <hamohammed.sa@gmail.com> Signed-off-by:
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