- 16 Jul, 2022 9 commits
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Srinivasa Rao Mandadapu authored
Move wcd specific pin conf to common file to support various herbronie variant boards and to avoid duplicate nodes in dts files. Signed-off-by:
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1657197381-1271-1-git-send-email-quic_srivasam@quicinc.com
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Marijn Suijten authored
These voltages are not a multiple of the given step-size 8000 (with base voltage 1664000) in pm8998_pldo, resulting in PLDO regulators l18 and l22 failing to validate and in turn not probing the rpm-pm8998-regulator driver: l18: unsupportable voltage constraints 2856000-2848000uV qcom_rpm_smd_regulator rpm-glink:rpm-requests:pm8998-regulators: l18: devm_regulator_register() failed, ret=-22 Round the voltages down for the sake of erring on the safe side, leaving a comment in place to document this discrepancy wrt downstream sources. Fixes: 390883af ("arm64: dts: qcom: msm8998: Introduce support for Sony Yoshino platform") Reported-by:Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
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Marijn Suijten authored
It seems the SM6350_CX definition was temporarily replaced with its literal value 0 in 1797e1c9 ("arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes") to prevent a dependency on the qcom-rpmpd.h header patch being available prior to this DT patch being applied, similar to c23f1b77 ("arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX"). However, unlike the revert of that in the sm6125 tree the next merge window around in a90b8adf ("Revert "arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX""), this has not yet happened for sm6350: replace them back now that the definitions are definitely available. Signed-off-by:
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Robert Marko authored
Add interrupt-parent to the SoC DTSI to avoid duplicating it in each board DTS file. Remove interrupt-parent from existing board DTS files. Signed-off-by:
Robert Marko <robimarko@gmail.com> Signed-off-by:
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Robert Marko authored
Add #size-cells and #address-cells to the SoC DTSI to avoid duplicating the same properties in board DTS files. Remove the mentioned properties from current board DTS files. Signed-off-by:
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Dmitry Baryshkov authored
Rename DPU device node to display-controller@ae01000 to follow the DPU schema. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Rename DPU device node to display-controller@ae01000 to follow the DPU schema. Signed-off-by:
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Dmitry Baryshkov authored
Rename DPU device node to display-controller@ae01000 to follow the DPU schema. Signed-off-by:
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Robert Marko authored
APCS now has support for providing the APSS clocks as the child device for IPQ8074. So, add the required DT node for it as it will later be used as the CPU clocksource. Signed-off-by:
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- 13 Jul, 2022 1 commit
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Bjorn Andersson authored
The timer node needs ranges specified to map the 1-cell children to the 2-cell address range used in /soc. This addition never made it into the patch that was posted and merged, so add it now. Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220707160858.3178771-1-bjorn.andersson@linaro.org
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- 08 Jul, 2022 4 commits
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Johan Hovold authored
Fix up the DP PHY node which had the wrong unit address. Signed-off-by:
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Johan Hovold authored
Fix the usb_0 HS PHY reference clock which was mistakingly replaced with the first usb_2 PHY clock. Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
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Johan Hovold authored
The recent commit that dropped the PCIe PHY clock index failed to update the PCIe node reference. Fixes: 531c738f ("arm64: dts: qcom: sc7280: drop PCIe PHY clock index") Reported-by:
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Mauro Carvalho Chehab authored
This document was added without placing it at arm book. Fixes: 59228d3b ("dt-bindings: Document how Chromebooks with depthcharge boot") Signed-off-by:
Mauro Carvalho Chehab <mchehab@kernel.org> Reviewed-by:
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- 07 Jul, 2022 26 commits
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Johan Hovold authored
Clean up the PCIe PHY node by renaming the wrapper node and grouping the child node properties. Signed-off-by:
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Johan Hovold authored
Clean up the PCIe PHY nodes by using a non-empty ranges property. Signed-off-by:
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Johan Hovold authored
The QMP UFS PHY provides more than one symbol clock and would need an index to differentiate the clocks, but none of this is described by the binding currently. Drop the incorrect '#clock-cells' property for now. Signed-off-by:
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Johan Hovold authored
The QMP UFS PHY provides more than one symbol clock and would need an index to differentiate the clocks, but none of this is described by the binding currently. Drop the incorrect '#clock-cells' property for now. Signed-off-by:
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Johan Hovold authored
The QMP UFS PHY provides more than one symbol clock and would need an index to differentiate the clocks, but none of this is described by the binding currently. Drop the incorrect '#clock-cells' property for now. Signed-off-by:
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Johan Hovold authored
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by:
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Johan Hovold authored
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by:
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Johan Hovold authored
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by:
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Johan Hovold authored
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by:
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Johan Hovold authored
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by:
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Johan Hovold authored
Add the missing '#clock-cells' properties to the PCIe QMP PHY nodes. Signed-off-by:
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Johan Hovold authored
The QMP PCIe PHY provides a single clock so drop the redundant clock index. Signed-off-by:
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Douglas Anderson authored
This reverts commit afcbe252. The commit in question caused my sc7280-herobrine-herobrine-r1 board not to boot anymore. This shouldn't be too surprising since the driver is relying on the name "cqhci". The issue seems to be that someone decided to change the names of things when the binding moved from .txt to .yaml. We should go back to the names that the bindings have historically specified. For some history, see commit d3392339 ("mmc: cqhci: Update cqhci memory ioresource name") and commit d79100c9 ("dt-bindings: mmc: sdhci-msm: Add CQE reg map"). Fixes: afcbe252 ("arm64: dts: qcom: Fix 'reg-names' for sdhci nodes") Signed-off-by:
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Dmitry Baryshkov authored
Add the (required) vdss-supply property to the DSI PHY node. Signed-off-by:
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Dmitry Baryshkov authored
To ease merging of bindings and dts files, the constants were replaced with numeric values. Change them back to defined constants. While we are at it, fix the indentation of these clocks properties to follow established guidelines. Signed-off-by:
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Dmitry Baryshkov authored
Add missing DSI clock assignments to properly use DSI PHY clocks as DSI byte and pixel clock parents. Signed-off-by:
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Robert Marko authored
Add reset to SDHCI controller so it can be reset to avoid timeout issues after software reset due to bootloader set configuration. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
Add device node for CPU-memory BWMON device (bandwidth monitoring) on SDM845 measuring bandwidth between CPU (gladiator_noc) and Last Level Cache (memnoc). Usage of this BWMON allows to remove fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high memory throughput even with lower CPU frequencies. Co-developed-by:
Thara Gopinath <thara.gopinath@gmail.com> Signed-off-by:
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Robert Marko authored
The ARM timer is usually considered not part of SoC node, just like other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning: arch/arm64/boot/dts/qcom/ipq8072-ax9000.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: -
Kuogee Hsieh authored
Both vdda-1p2-supply and vdda-0p9-supply regulators are controlled by dp combo phy. Therefore remove them from dp controller. Signed-off-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by:
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Abel Vesa authored
Switch from the flat PC idle states of sdm845 to OSI hierarchical idle states. The exceptions are the cheza plaftorms, which need to remain with PC idle states. So in order allow all the other platforms to switch, while cheza platforms to remain the same, replace the PC idle states with the OSI ones in the main SDM845 dtsi, and then override the inherited OSI states with PC ones, delete inherited psci cpus nodes, domain idle states and power domain properties. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Tested-by:
Steev Klimaszewski <steev@kali.org> Acked-by:
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David Heidelberg authored
First device specific compatible, then general one. Reviewed-by:
David Heidelberg <david@ixit.cz> Signed-off-by:
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Anton Bambura authored
Adds initial support for the LG G7 (judyln) and LG V35 (judyp) phones. Currently supported features: - Display via simplefb (panel driver is WIP) - Keys - Micro SD card - Modem (not tested much, but initialises) - UFS (crashes during intensive workloads, may need quirks) - USB in peripheral mode Notable missing features: - Enabling WiFi causes a remoteproc crash, so it's disabled here. Needs to be debugged - ideas welcome! Signed-off-by:
Anton Bambura <jenneron@protonmail.com> Signed-off-by:
Stefan Hansson <newbie13xd@gmail.com> Tested-by:
Gregari Ivanov <llamashere@posteo.de> Signed-off-by:
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Dmitry Baryshkov authored
Add XO clock source to the RPM clock controller. Signed-off-by:
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Dmitry Baryshkov authored
Add missing GCC clock sources. This includes PCIe and USB PIPE and UFS symbol clocks. Signed-off-by:
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Dmitry Baryshkov authored
The commit 82d61e19 ("arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP PHY child node") moved the '#clock-cells' properties to the child nodes. However it missed the fact that the property must have been set to <0> (as all pipe clocks use of_clk_hw_simple_get as the xlate function. Also the mentioned commit didn't add '#clock-cells' properties to second and third PCIe PHY nodes. Correct both these mistakes: - Set '#clock-cells' to <0>, - Add the property to pciephy_1 and pciephy_2 nodes. Fixes: 82d61e19 ("arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP PHY child node") Signed-off-by:
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