- 21 Jun, 2019 40 commits
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Hawking Zhang authored
This is to differentiate rlc backdoor autoload from rlc frontdoor autoload Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored
Instead of putting toc into driver source code, the toc will be part of psp_sos fw. Driver need to get and parse it from psp fw Signed-off-by:
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Hawking Zhang authored
psp_firmware_header_v1_1 is used for psp sos with build-in toc Signed-off-by:
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Hawking Zhang authored
Table Of Content (TOC) is used by RLC to auto load gc firmwares. PSP need to parse the toc to calculate the tmr size needed and load gc firmwares to tmr for RLC to auto load them finally Signed-off-by:
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Tao Zhou authored
Add psp 11.0 code for navi10. psp 11.0 is not enabled for now. Will enable it when psp 11.0 firmware is available. Signed-off-by:
Tao Zhou <Tao.Zhou1@amd.com> Reviewed-by:
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Huang Rui authored
For bring up. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Le.Ma authored
Add another firmware load type AMDGPU_FW_LOAD_RLC_AUTO to support firmware autoloading new feature in gfx10. This flag can be leveraged for future engines that need autoload fw. Signed-off-by:
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Le.Ma authored
Allocate a visible framebuffer to store all gfxip ucodes as the format of TOC. Signed-off-by:
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Hawking Zhang authored
IH is the interrupt handler block. v1: add initial ih support (Ray) v2: add dummy prescreen iv function for navi10 (Hawking) v3: squash in additional updates (Alex) Signed-off-by:
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Hawking Zhang authored
interrupt source packet definitions for the display block (DCN). Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Signed-off-by:
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Hawking Zhang authored
Add the interrupt source packet definitions. v2: update (Alex) Signed-off-by:
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Hawking Zhang authored
Add the interrupt source packet definitions. Signed-off-by:
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Hawking Zhang authored
Add the interrupt source packet definitions. Signed-off-by:
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Hawking Zhang authored
GMC in the GPU memory controller. v1: add place holder and initial basic implementation (Ray) v2: retire unused amdgpu_gart_set_defaults (Hawking) v3: re-work get_vm_pde function (Hawking) v4: replace legacy amdgpu_vram/gtt_location with amdgpu_gmc_vram/gtt_location (Hawking) v5: squash in updates (Alex) v6: use get_vbios_fb_size (Alex) Signed-off-by: -
Hawking Zhang authored
mmhub is the memory controller hub for multi-media (VCN). v1: add place holder and initial functions (Ray) v2: replace legacy amdgpu_mc structure with amdgpu_gmc (Hawking) v3: switch to use amdgpu_gmc_pd_addr (Hawking) v4: squash in updates (Alex) Signed-off-by:
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Hawking Zhang authored
gfxhub is the memory controller hub for gfx and sdma. v1: add place holder and initial basic functions (Ray) v2: replace the refernce to legacy mc structure with gmc structure remove the direct use of gart.table_addr (Hawking) v3: switch to use amdgpu_gmc_pd_addr (Hawking) v4: squash in updates (Alex) Signed-off-by: -
Jack Xiao authored
Due to GCR change from navi10, the PTE encoding of PRT needs change VSCTL = 01111 (was 0XX1X). Signed-off-by:
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Hawking Zhang authored
To differentiate the mtypes across asics. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Hawking Zhang authored
The MTYPE filed moves from bits 58:57 to 50:48 for NV10 And the size of MTYPE field is now 3bits Signed-off-by:
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Jack Xiao authored
Enable athub2 clock gating and light sleep Signed-off-by:
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Hawking Zhang authored
Add new flag for IH (interrupt handler) clockgating. Signed-off-by:
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Hawking Zhang authored
HDP 5.0 supports SRAM power gating. all the LS (Light Sleep)/ DS (Deep Sleep)/SD (Shut Down) modes are supported. However, only one of these modes can be enabled at one time. There is no dynamic power mode switch support. clock/power gating has to be disabled before making any power mode change. Signed-off-by:
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Hawking Zhang authored
mqd is the memory queue descriptor for gfx and compute. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Jack Xiao authored
VDDGFX requires gfx queue to be installed via MAP_QUEUES packet. Hence, enable async gfx ring by default. Signed-off-by:
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Hawking Zhang authored
0 means disable async_gfx_ring and is the default setting 1 means enable async_gfx_ring Signed-off-by:
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Hawking Zhang authored
Navi10 has 2 gfx pipe and need to enable gfx eop interrupt per pipe, instead of enable eop int for all gfx pipes at one time. Signed-off-by:
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Jack Xiao authored
CP introduced a special unmap_queues packet for gfx preemtion. Acked-by:
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Hawking Zhang authored
move common code to amdgpu_gfx_enable_kcq,so this function can be shared with gfx8 and gfx9 Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
so can be shared with gfx8 and gfx9 Reviewed-by:
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Rex Zhu authored
kiq can support 4 pm4 scheduler packets set_resource, map_queues, unmap_queues, query_status. Reviewed-by:
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Hawking Zhang authored
The function now will create mqd bos for both gfx queue and compute queue Signed-off-by:
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Hawking Zhang authored
Similar to what we do for compute already. Signed-off-by:
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Hawking Zhang authored
currently, amdgpu will owns the first gfx queue of each pipe they are: me:0 pipe:0 queue:0 me:0 pipe:1 queue:0 Signed-off-by:
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Hawking Zhang authored
Update the structure for gfx10. Signed-off-by:
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Hawking Zhang authored
gfx10 allows to only upload me jumptable while save the whole me image at gtt memory. v2: program CP_ME_IC_BASE_CNTL to default value v3: switch to use amdgpu_bo_create_reserved to create me fw bo v4: split common code from gfx10 code Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Hawking Zhang authored
gfx10 allows to only upload ce jumptable while save the whole ce image at gtt memory. v2: program CP_CE_IC_BASE_CNTL to default value v3: switch to use amdgpu_bo_create_reserved to create ce fw bo v4: split common code from gfx10 code Signed-off-by:
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Hawking Zhang authored
gfx10 allows to only upload pfp jumptable while save the whole pfp image at gtt memory. v2: program CP_PFP_IC_BASE_CNTL to default value v3: switch to use amdgpu_bo_create_reserved to create pfp fw bo v4: split common code from gfx10 code Signed-off-by:
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Hawking Zhang authored
nbio handles bus io functionality. v1: add place holder and initial basic nbio v2.3 functions (Ray) v2: implements and expose all functions in format of nbio_v2_3_funcs (Hawking) v3: squash in updates (Alex) v4: whitespace fix (Alex) Signed-off-by:
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Leo Liu authored
For Navi10 VCN2.0, the engine supports Doorbell Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Hawking Zhang authored
Driver will get channel_number and channel_width from vram_info table, then calculate vram_width by multiply channel_number by channel_width Signed-off-by:
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