- 06 Dec, 2019 1 commit
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Andrey Grodzovsky authored
BACO feature must be kept enabled to allow entry into BACO state in SMU during runtime suspend. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Tested-by:
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- 05 Dec, 2019 39 commits
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Nicholas Kazlauskas authored
[Why] To quickly validate whether DMCUB is running and accepting commands for offload testing we want to intercept a common sequence as part of modeset programming. [How] OTG enable will cause the most impact in terms of golden register changes and it's a single register write. This approach was previously done in dcn10 code when it was shared with dcn20 but it wasn't ported over to the dcn20 code. Port over start, execute and wait sequence into dcn20_optc. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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abdoulaye berthe authored
[Why] When setting lttpr mode, the new mode to bet is not logged properly. [How] Update log message to show the right mode. Signed-off-by:
abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
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Dmytro Laktyushkin authored
In preparation for further changes Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] It seems always request passive flip on RN due to incorrect compare clock state to determine optization. [How] Instead of calling memcmp, compare clock state member to determine the condition. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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George Shen authored
[Why] When a timeout occurs after a DEFER, some devices require more retries than in the case of a regular timeout. [How] In a timeout occurrence, check whether a DEFER has occurred before the timeout and retry MAX_DEFER_RETRIES retries times instead of MAX_TIMEOUT_RETRIES. Signed-off-by:
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Krunoslav Kovac authored
[Why] Currently we require HDR_MULT >= 1.0 There are scenarios where we need < 1.0 [How] Only guard against 0 - it will black-screen image. It is up to higher-level logic to decide what HDR_MULT values are allowed in each particular case. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Reza Amini authored
[Why] Need support for more color management in 10bit surface. [How] Provide support for DePQ for 10bit surface Signed-off-by:
Reza Amini <Reza.Amini@amd.com> Reviewed-by:
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Eric Yang authored
Value obtained from DV is not allowing 8k60 CTA mode with DSC to pass, after checking real value being used in hw, find out that correct value is 3600, which will allow that mode. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Amanda Liu authored
[Why] Screen tearing is present in tests when setting the frame rate to certain fps [How] Revert previous optimizations for low frame rates. Signed-off-by:
Amanda Liu <amanda.liu@amd.com> Reviewed-by:
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Aric Cyr authored
[Why] Cursor position needs to take into account plane scaling as well. [How] Translate cursor coords from stream space to plane space. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Anthony Koo authored
[Why] It is causing green Line at the bottom of SDR 480p MPO playback [How] Limit workaround to vertical > 512 Signed-off-by:
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Wenjing Liu authored
dc needs to expose its internal dsc policy. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
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Wenjing Liu authored
[why] add_dsc_to_stream_resource could be called for validation. Failing validation is completely fine. However failing it inside commit streams is bad. This code could be triggered for both contexts. The function itself cannot distinguish the caller, which makes it impossible to output the log only in the meaningful case (commit streams). Signed-off-by:
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Wenjing Liu authored
[why] Need to support 6 bpp for 420 pixel encoding only. [how] Add a dc function to determine what bpp range can be supported for given pixel encoding. Signed-off-by:
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Noah Abradjian authored
[Why] I was advised that we don't need this call of program_front_end, as earlier and later calls in the same sequence are sufficient. [How] Remove first call of program_front_end in dc_commit_state_no_check. Signed-off-by:
Noah Abradjian <noah.abradjian@amd.com> Reviewed-by:
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Noah Abradjian authored
[Why] I was advised that we may need to check for mpcc idle in more cases than just when opp_changed is true. Also, mpcc_inst is equal to pipe_idx, so remove for loop. [How] Remove opp_changed flag check and mpcc_inst loop. Signed-off-by:
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abdoulaye berthe authored
[Why] When training with repeater the aux read interval must be set to repeater specific aux_red_interval. This value is always 100us for CR. [How] Check for repeater when setting the aux_rd_interval in channel equalization. Use the right offset in the aux_rd_interval array Signed-off-by:
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Noah Abradjian authored
[Why] MPCC programming was being missed during certain split pipe enables due to full_update flag not being true. This caused a momentary flash on half the screen. After discussion, determined we should not have that flag check within update_mpcc, as it should always perform full programming when called. [How] Remove flag check. We call update_blending within insert_plane, so we do not need to replace its call from the if block. Signed-off-by:
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Joseph Gravenor authored
[Why] DF team has produced more optimized sr latency numbers, for lpddr4 [How] change the sr laency in the lpddr4 wm table to the new latency number Signed-off-by:
Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Scratch registers are limited on the DMCUB and we have an expanding list of state to track between driver and DMCUB. [How] Place shared state in cache window 6. The cache window size is aligned to the size of the cache line on the DMCUB to make it easy to invalidate. The shared state is intended to be read only from driver side so it's been marked as const. The use of volatile is intentional. The memory for the shared firmware state is memory mapped from the framebuffer memory. The DMCUB will flush its cache after modifying the region. There's no way for x86 to known whether this data is stale or not so we want to intentionally disable optimization to force the read at every access. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Commands will be considered a stable ABI between driver and firmware. Commands are also split between DC commands, DAL feature commands, and VBIOS commands. Commands are currently not designated to a specific ID and the enum does not provide a stable ABI. We currently group all of these into a single command type of 8-bits. With the stable ABI consideration in mind it's not unreasonable to run out of command IDs. For cleaner separation and versioning split the commands into a main type and a subtype. [How] For commands where performance matters (like reg sequences) these are still considered main commands. Sub commands will be split by ownership/feature. Update existing command sequences to reflect new changes. Signed-off-by:
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Mikita Lipski authored
[why] The function is expected to return instance of the timing generator therefore we shouldn't be returning boolean in integer function, and we shouldn't be returning zero so changing it to -1. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Hugo Hu authored
[Why] The link setting will be modify after disable phy and due to DP Compliance Fails. [How] Save and resotre link setting for disable link phy when link retraining. Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
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Anthony Koo authored
[Why] We want to know DP protocol version [How] In DC create we initialize a cap to indicate the max DP protocol version supported Signed-off-by:
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Joseph Gravenor authored
[Why] DF team has produced more optimized latency numbers, for lpddr4 [How] change the p-state laency in the lpddr4 wm table to the new latency number Signed-off-by:
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Reza Amini authored
[Why] Need support for more color management in 10bit surface. [How] Provide support for DePQ for 10bit surface Signed-off-by:
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Nikola Cornij authored
[why] During mode transition steer fifo could overflow. Quite often it recovers by itself, but sometimes it doesn't. [how] Add steer fifo reset before unblanking the stream. Also add a short delay when resetting dig resync fifo to make sure register writes don't end up back-to-back, in which case the HW might miss the reset request. Signed-off-by:
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Dmytro Laktyushkin authored
Bring this calculation in line with HW programming guide. Signed-off-by:
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Michael Strauss authored
[WHY] Previous Renoir chroma viewport workaround fixed an MPO flicker by increasing the chroma viewport size. However, when the MPO plane is rotated 180 degrees, the viewport is read in reverse. Since the workaround increases viewport size, when reading in reverse it causes a vertical chroma offset. [HOW] Pass rotation value to viewport set functions Temporarily disable the chroma viewport w/a when hubp is rotated 180 degrees Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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abdoulaye berthe authored
Signed-off-by:
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Brandon Syu authored
[Why] The variable mismatch assignment error. [How] To use uint32_t replace it. Signed-off-by:
Brandon Syu <Brandon.Syu@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Leo (Hanghong) Ma authored
[why] DP spec requires 1000 symbols delay between the end of link training and enabling FEC in the stream. Currently we are using 1 miliseconds delay which is not accurate. [how] One lane RBR should have the maximum time for transmitting 1000 LL codes which is 6.173 us. So using 7 microseconds delay instead of 1 miliseconds. Signed-off-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Reviewed-by:
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Aric Cyr authored
Signed-off-by:
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Eric Yang authored
[Why] Before was using HW counter value to determine the dprefclk. Which take into account ss, but has large variation, not good enough for generating audio dto. Also, the bios parser code to get the ss percentage was not working. [How] After this change, dprefclk is hard coded, same as on RV. We don't expect this to change on Renoir. Modified bios parser code to get the right ss percentage. Signed-off-by:
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Joseph Gravenor authored
[Why] new sr and pstate latencies are optimized for the case when we are not using lpddr4 memory [How] have two different wm tables, one for the lpddr case and one for non lpddr case Signed-off-by:
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David Galiffi authored
[Why] In dc_link_is_dp_sink_present, if dal_ddc_open fails, then dal_gpio_destroy_ddc is called, destroying pin_data and pin_clock. They are created only on dc_construct, and next aux access will cause a panic. [How] Instead of calling dal_gpio_destroy_ddc, call dal_ddc_close. Signed-off-by:
David Galiffi <David.Galiffi@amd.com> Reviewed-by:
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Joseph Gravenor authored
[Why] When video_memory_type bw_params->vram_type is assigned, wedistinguish between Ddr4MemType and LpDdr4MemType. Because of this we will never report that we are using LpDdr4MemType and never re-purpose WM set D [How] populate bios integrated info for renoir by adding the revision number for renoir and use that integrated info table instead of of asic_id to get the vram type Signed-off-by:
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Nicholas Kazlauskas authored
[Why] On dcn21 this is programmed for tracebuffer support but isn't being programmed on dcn20. DMCUB execution hits an undefined address 65000000 on tracebuffer access. [How] Program CW5. Signed-off-by:
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