The HREFv60 variant of the MOP500 family of boards remove the
external GPIO expander and route these pins back to some of the
readily available internal GPIO pins instead.

Based on a patch by Bibek Basu <bibek.basu@stericsson.com> for
an internal kernel version.

Cc: Bibek Basu <bibek.basu@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

This will centralize all GPIO pin muxing for the different boards
in the MOP500 family to a single file. It also kills off the
deprecated support for the ED (Early Drop) ASIC, this should
never be spotted in the open and ST-Ericsson have internally
deprecated this hardware.
Signed-off-by: Bibek Basu <bibek.basu@stericsson.com>
[Rebasing and kill old ASIC support]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Split off pin definitions for the MOP500 board family to its
own file.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The compiler warns that [rf]wimsc may be used uninitialized in
this function - the warning is actually false since the uses are
in identical if()-clauses, but it can't hurt very much to read
out the values to be modified early anyway and rid the warning.

Cc: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The NOMADIK_GPIO_PM config option is disabled by default, not user visible,
and never selected by any other option: the code is therefore unused. The
GPIO registers need not be saved and restored since their values are
preserved when vAPE (on DB8500) is powered down.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Reviewed-by: Jonas Aberg <jonas.aberg@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

This patch fixes a bug when setting SLPM register for DB8500.
When calling__nmk_gpio_set_slpm(...) offset to GPIO is now used
instead of the GPIO number itself.
Signed-off-by: Rikard Olsson <rikard.p.olsson@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Setting pinmux alternative C for a GPIO pin is actually not
so easy since it ivolves setting value "1" in two registers,
and since the combined result will take effect for intermediate
values (01 or 10) this will cause glitches while you wrote one
register but have not yet written the other.

This patch implements a series of kludges including an optional
machine-specific callback to avoid glitches when changing pin
mux mode to alternative C.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Coverity found that we were checking an unsigned variable for
>= zero. Type it correctly so that the check works as intended.
Signed-off-by: Virupax Sadashivpetimath <virupax.sadashivpetimath@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Suspend/resume didn't take care of pull-up and pull-down
settings and writing back the DAT register at resume can
change pull up/down settings, depending on pin input value.
Output values are now also restored.
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

When GPIOs wake up the system from sleep mode, the normal GPIO interrupt
handler does not hit and the normal interrupt status register does not
contain the status. Instead the secondary GPIO handler does, and the
interrupt status needs to be retrieved from the wakeup status saved by
the suspend/resume code.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
[Added constant 32-pin assignment in platform data]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

This will configure the platform data for the PL011, PL022
and PL180 (derivate) PrimeCells found in the Ux500 to use DMA
with the generic DMA engine for DMA40.
Signed-off-by: Per Forlin <per.forlin@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

This will configure the platform data for the PL180, PL011 and
PL022 PrimeCells found in the U300 to use DMA with the generic
PrimeCell DMA engine for COH 901 318.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The mmci driver can handle a GPIO pin for card detect, using
IRQs and all just fine, so switch to using that. Delete the
old bogus input device hack, if userspace need to detect
MMC cards it should use udev like everyone else.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

- DMA tx and rx maps for usb channels are set to be configured at
  runtime
- MUSB is enabled with soc specific base address, irq and dma
  configurations
Signed-off-by: Mian Yousaf Kaukab <mian-yousaf.kaukab@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

- DMA tx and rx maps for usb channels are set to be configured at
  runtime
- GPIO configurations for usb are added
- MUSB is enabled with soc specific base address, irq and dma
  configurations
Signed-off-by: Mian Yousaf Kaukab <mian-yousaf.kaukab@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

MUSB driver has been updated to separate out BSP layer
from its generic parts, as separate driver. This patch
configures the clock with the new platform driver name.
Signed-off-by: Mian Yousaf Kaukab <mian-yousaf.kaukab@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

USB resources and DMA40 configurations are dynamically with
the data provided in ux500_add_usb() call. Though only DMA40
configurations differ between U8500 and U5500 (USB resource
are common between them).
Signed-off-by: Mian Yousaf Kaukab <mian-yousaf.kaukab@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The levelshifter pins were set to inverted values, fix this up.
Signed-off-by: Philippe Langlais <philippe.langlais@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The clock speed for the SD/MMC clock was incorrect, rectify it.
Signed-off-by: Philippe Langlais <philippe.langlais@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Signed-off-by: Philippe Langlais <philippe.langlais@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Proximity sensor is managed as an input event (SW_PROXIMITY).
Signed-off-by: Philippe Langlais <philippe.langlais@linaro.org>
[Named GPIO pin]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

We register keypads per-UIB now, remove this.

Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The U8500 UIB contains a Synaptics RMI touchpanel and
a matrix keyboard via the TC35893 port expander device.
Signed-off-by: Sundar Iyer <sundar.iyer@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The ST-UIB contains a matrix keypad interfaced with the
STMPE1601 port expander and a ROHM BU2101 touch panel.
Signed-off-by: Sundar Iyer <sundar.iyer@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Add support for dynamic detection of the UIB used (at the cost of one i2c error
on the lesser-used UIB) and also provide an override via a command line
parameter if needed.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Sundar Iyer <sundar.iyer@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Include ab8500 regulators for DB8500 SoC by default
and fix build issues
Signed-off-by: Sundar Iyer <sundar.iyer@stericsson.com>
[Small fixup for changed boardfiles]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Try to make the regulators a little bit more useful by adding some
of the most basic consumers we're going to have in the end.

Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Rabin Vincent <rabin@rab.in>
Cc: Naveen Kumar Gaddipati <naveen.gaddipati@stericsson.com>
Cc: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

This adds the PMU resources necessary to get perf working with
the DB5500 ASIC.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/tglx/linux-2.6-tcc into devel-stable

There are two dividers used to derive bus clock from system clock:
system clock is divided by SCKDIV+1, then by BCKDIV+1. SCKDIV divider
has been ignored up to now, which is no problem as long as it is 0.

Take SCKDIV into account for bus clock calculation.
Signed-off-by: Oskar Schirmer <oskar@linutronix.de>
Cc: bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

Remove double definition of ACLKUSBH, change parameter name in
root_clk_disable, as there is no reason to have a different name than
in root_clk_enable.

No functional change.
Signed-off-by: Oskar Schirmer <oskar@linutronix.de>
Cc: bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

There is no reason why in case of PLL2 the configuration register
should be read twice, while for PLL0/1 using the value previously read
is used. Do the same for PLL2.
Signed-off-by: Oskar Schirmer <oskar@linutronix.de>
Cc: bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

The calculation of the best divider value for a requested clock rate
always returned a value that was slightly too large. It was also not
protected against possible divisions by zero.

Request for very low, but non zero rates would cause the ACLK divisor
field to overflow. Catch this situation by using the maximum value.

The internal function aclk_set_rate() calculates the correct divider
value, but doesn't write it back to the register. Add the write back.
Signed-off-by: Hans J. Koch <hjk@linutronix.de>
Signed-off-by: Oskar Schirmer <oskar@linutronix.de>
Cc: bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

The evaluation board is driven with 1.2V core voltage, so system clock
must not exceed 192 MHz, bus clock must not exceed 110 MHz. Choose
appropriate values and set DTCMWAIT accordingly. Adapt UART setting to
avoid console log interruption and wait for the specified locking time
of 300us to pass.
Signed-off-by: Oskar Schirmer <oskar@linutronix.de>
Cc: bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

If NAND is enabled we better have the include around.
Signed-off-by: Oskar Schirmer <oskar@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>