- 05 Dec, 2018 1 commit
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Nicholas Mc Guire authored
devm_kasprintf() may return NULL on failure of internal allocation thus the assignment to .label is not safe if not checked. On error npcm7xx_gpio_of() returns negative values so -ENOMEM in the (unlikely) failure case of devm_kasprintf() should be fine here. Signed-off-by:
Nicholas Mc Guire <hofrat@osadl.org> Fixes: 3b588e43 ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver") Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 26 Nov, 2018 2 commits
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Shawn Guo authored
Let's add "qcom,pms405-gpio" to match table, as commit ed80f6eb ("dt-bindings: pinctrl: qcom-pmic-gpio: Add pms405 support") already adds the compatible. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Shawn Guo authored
Rather than gpio1-gpio11 for pms405, there are 12 GPIOs for pms405. But gpio1, gpio9 and gpio10 are not available. Fix the bindings doc to make it correct for pms405. Fixes: ed80f6eb ("dt-bindings: pinctrl: qcom-pmic-gpio: Add pms405 support") Signed-off-by:
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- 25 Nov, 2018 3 commits
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.21-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.21 - Fix VIN (Video IN) versioned groups on R-Car V2H, H3, and M3-W, - Add I2C[0-3], DU1, VIN, QSPI1, and SDHI pin groups on RZ/G1C, - Add audio, SDHI, VIN, HSCIF, and CAN(FD) support on R-Car E3, - Add QSPI pin groups on R-Car V3M and V3H, - Add VIN and CAN(FD) pin groups on R-Car M3-N, - Add I2C[035] pin groups on R-Car H3 and M3-W, - Add pinctrl and GPIO support for the new RZ/A2M (R7S9210) SoC, - Small cleanups, - Maintainership updates.
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Mesih Kilinc authored
The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a pin controller like other SoCs from Allwinner. Add support for it. Signed-off-by:
Mesih Kilinc <mesihkilinc@gmail.com> Acked-by:
Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by:
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Mesih Kilinc authored
Add compatible string for Allwinner suniv F1C100s SoC's pinctrl. Signed-off-by:
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- 23 Nov, 2018 2 commits
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Chris Brandt authored
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs. Signed-off-by:
Chris Brandt <chris.brandt@renesas.com> Reviewed-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Chris Brandt authored
Add device tree binding documentation and header file for Renesas R7S9210 (RZ/A2) SoCs. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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- 20 Nov, 2018 1 commit
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Dmitry Shifrin authored
Add the QSPI{0|1} pins/groups/functions to the R8A77980 PFC driver. [Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/ SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to be in the alphanumeric order, removed unneeded empty lines, renamed the patch.] Signed-off-by:Dmitry Shifrin <dmitry.shifrin@cogentembedded.com> Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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- 19 Nov, 2018 21 commits
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Rob Herring authored
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: linux-mediatek@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by:
Sean Wang <sean.wang@kernel.org> Signed-off-by:
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Evan Green authored
Add PM suspend callbacks to the msm core driver that select the sleep and default pinctrl states. Then wire those callbacks up in the sdm845 driver, for those boards that may have GPIO hogs that need to change state during suspend. Signed-off-by:
Evan Green <evgreen@chromium.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Ryder Lee authored
This updates bindings for MT7629 pinctrl driver. Signed-off-by:
Ryder Lee <ryder.lee@mediatek.com> Reviewed-by:
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Ryder Lee authored
This adds MT7629 pinctrl driver based on MediaTek pinctrl-moore core. Signed-off-by:
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A.s. Dong authored
After patch b96eea71 ("pinctrl: fsl: add scu based pinctrl support"), NO_PAD_CTL pads map are not skipped anymore which results in a possible memory corruption. As we actually only need to create config maps for SCU pads and MMIO pads which are not using the default config (a.k.a IMX_NO_PAD_CTL), so let's add a proper check before creating the config maps. And during MMIO pads parsing, we also need update the list_p point as SCU case to ensure the pin data next parsed is correct. Cc: Linus Walleij <linus.walleij@linaro.org> Fixes: b96eea71 ("pinctrl: fsl: add scu based pinctrl support") Reported-by:
Martin Kaiser <martin@kaiser.cx> Suggested-by:
Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by:
Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by:
Kevin Hilman <khilman@baylibre.com> Signed-off-by:
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Saravanan Sekar authored
Add pinctrl and gpio driver for Actions Semi S700 SoC. The driver supports pinctrl, pinmux, pinconf, gpio and interrupt functionalities through a range of registers common to both gpio driver and pinctrl driver. Signed-off-by:
Parthiban Nallathambi <pn@denx.de> Signed-off-by:
Saravanan Sekar <sravanhome@gmail.com> Acked-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Saravanan Sekar authored
Add pinctrl and pio bindings for Actions Semi S700 SoC. Signed-off-by:
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Saravanan Sekar authored
pad control for s900 and s700 are differs in number of pull control configuraions s900 has 4 pull controls - high impedence, pull up, pull down, repeater s700, s500 has 2 pull controls - pull up and pull down so pad control configuration has to SoC specific, moved out from pinctrl common to s900 specific. Signed-off-by:
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Saravanan Sekar authored
Move generic defines common to the Owl family out of S900 driver. Signed-off-by:
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Benjamin Gaignard authored
If a hwspinlock if defined in device tree use it to protect configuration registers. Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by:
Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by:
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Benjamin Gaignard authored
Add hwlocks as optional property Signed-off-by:
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Takeshi Kihara authored
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77990 SoC. Signed-off-by:Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@gmail.com> [geert: Move canfd from common to automotive] Signed-off-by:
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Takeshi Kihara authored
This patch adds CAN{0,1} pins, groups and functions to the R8A77990 SoC. Signed-off-by: -
Takeshi Kihara authored
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77965 SoC. Signed-off-by: -
Takeshi Kihara authored
This patch adds CAN{0,1} pins, groups and functions to the R8A77965 SoC. Signed-off-by: -
Takeshi Kihara authored
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by:Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by:
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Takeshi Kihara authored
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 ES1.x SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by: -
Takeshi Kihara authored
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by: -
Ulrich Hecht authored
Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs. Signed-off-by:
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Geert Uytterhoeven authored
The PINMUX_IPSR_MSEL2() and PINMUX_IPSR_PHYS() macros are unused, and will conflict with generic macros that are to be added. Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Takeshi Kihara authored
This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to the R8A77990 SoC. Signed-off-by:Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by:
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- 17 Nov, 2018 2 commits
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Heiko Stuebner authored
The rk3188 has pins that are not handled through the regular iomuxing for handling either nand-flash or an emmc and are set through only one specifal setting. So utilize the routing function to simply do that setting depending on one of the core nand/emmc signals that are actually regular pins handled through pinctrl. Signed-off-by:
Heiko Stuebner <heiko.stuebner@bq.com> Signed-off-by:
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Heiko Stuebner authored
Right now we expect the pin-rounting settings to be in the same area as the iomux setting itself. And while that seems to be true for all newer Rockchip socs, back in the wild west days of old this wasn't true. Nowadays pin settings in the GRF normally stay in the GRF and the same is true for pins configured from PMU registers. But old socs like the rk3188 really sprinkle pin settings somewhat randomly through both for its bank0. Therefore add the option to specify a location for the route setting, so that we can map older socs correctly. We'll keep "same" as the default, so that we only need to specify a location in the corner-cases described above. Signed-off-by:
David Wu <david.wu@rock-chips.com> Signed-off-by:
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- 16 Nov, 2018 2 commits
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Brian Masney authored
When attempting to setup up a gpio hog, device probing will repeatedly fail with -EPROBE_DEFERED errors. It is caused by a circular dependency between the gpio and pinctrl frameworks. If the gpio-ranges property is present in device tree, then the gpio framework will handle the gpio pin registration and eliminate the circular dependency. See Christian Lamparter's commit a86caa9b ("pinctrl: msm: fix gpio-hog related boot issues") for a detailed commit message that explains the issue in much more detail. The code comment in this commit came from Christian's commit. I did not test this change against any hardware supported by this particular driver, however I was able to validate this same fix works for pinctrl-spmi-gpio.c using a LG Nexus 5 (hammerhead) phone. Signed-off-by:
Brian Masney <masneyb@onstation.org> Reviewed-by:
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Stefan Wahren authored
Adopt the SPDX license identifier headers to ease license compliance management. Cc: Simon Arlott <simon@arlott.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by:
Eric Anholt <eric@anholt.net> Signed-off-by:
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- 15 Nov, 2018 5 commits
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Tomer Maimon authored
Modify GPIO direction setting in pin configuration function by using generic GPIO functions to set the GPIO direction instead of direct access to the GPIO direction register. Signed-off-by:
Tomer Maimon <tmaimon77@gmail.com> Tested-by:
Kun Yi <kunyi@google.com> Signed-off-by:
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Manivannan Sadhasivam authored
Add initial pinctrl driver for Mediatek MT6797 SoC supporting only GPIO and pinmux configurations. Tested-by:
Matthias Brugger <matthias.bgg@gmail.com> Acked-by:
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Manivannan Sadhasivam authored
Add devicetree bindings for Mediatek MT6797 SoC Pin Controller. Signed-off-by:
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Neil Armstrong authored
The GPIOX tsin_a pins wrongly uses the SDCard pinctrl bits, this patch completely removes these pins entries until we find out what are the correct bits and registers to be used instead. Fixes: 5a6ae9b8 ("pinctrl: meson-gxl: add tsin_a pins") Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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Olof Johansson authored
Fixes the following config-time warning: WARNING: unmet direct dependencies detected for EINT_MTK Depends on [n]: PINCTRL [=y] && (ARCH_MEDIATEK [=y] || COMPILE_TEST [=n]) && (PINCTRL_MTK [=n] || PINCTRL_MTK_MOORE [=n] || COMPILE_TEST [=n]) Selected by [y]: - PINCTRL_MTK_PARIS [=y] && PINCTRL [=y] && OF [=y] && (ARCH_MEDIATEK [=y] || COMPILE_TEST [=n]) Fixes: 80525098 ("pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings") Signed-off-by:
Olof Johansson <olof@lixom.net> Acked-by:
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- 13 Nov, 2018 1 commit
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Jacopo Mondi authored
Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car E3. Signed-off-by:
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