- 22 Mar, 2024 16 commits
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Xi Liu authored
[Why] The hard coded DPM states are only used to fix mismatch states numbers from FW. [How] Remove when not needed. Reviewed-by:
Sung joon Kim <sungjoon.kim@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Xi Liu <xi.liu@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicholas Kazlauskas authored
[Why] It's possible to skip parts of the eval and exit sequencing if we know whether DCN is in IPS2 already or if it's committed to going to idle and not in IPS2. [How] Skip IPS2 entry/exit if DMCUB is idle but the IPS2 commit is not set. Skip the eval delay if DMCUB is already in IPS2 since we know we need to exit. These are turned off by default. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] Cursor updates can be preempted by queued flips in some DMs. The synchronization model causes this to occur within the same thread at an intermediate level when we insert logs into the OS queue. Since this occurs on the same thread and we're still holding the lock (recursively) the cache is coherent. The exit sequence will run twice since we technically haven't finished the exit the first time, so we need a way to detect and avoid the reallow in the middle of this call to prevent the hang on the cursor update that was preempted. [How] Keep a counter that tracks the depth of the exit calls. Do not reallow until the counter is zero. Reviewed-by:
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Xi Liu authored
[Why and how] Bounding box clocks for DCN351 should be increased as per request Reviewed-by:
Swapnil Patel <swapnil.patel@amd.com> Acked-by:
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Chris Park authored
[Why] Disabling stream encoder invokes a function that no longer exists. [How] Check if the function declaration is NULL in disable stream encoder. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Chris Park <chris.park@amd.com> Tested-by:
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Natanel Roizenman authored
Increase Z8 watermark times from 210->250us and 320->350us. Reviewed-by:
Natanel Roizenman <natanel.roizenman@amd.com> Tested-by:
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Charlene Liu authored
[why] APU has different refclk as dGPU which is used for AUX_DPHY setup Reviewed-by:
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Yang Wang authored
add ras event id support for ACA. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Yang Wang authored
Because the UE Valid MCA count will only be cleared after reset, in order to avoid repeated counting of the error count, the aca bank is only updated once during ras isr. Signed-off-by:
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Yang Wang authored
retrieve umc odecc error count for aca umc v12.0 Signed-off-by:
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Mukul Joshi authored
Check cgroup permissions when returning DMA-buf info and based on cgroup info return the GPU id of the GPU that have access to the BO. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Natanel Roizenman authored
Added debug prints for zstate_support and StutterPeriod in dcn35_decide_zstate_support for testing. Reviewed-by:
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Dillon Varone authored
[WHY&HOW] Even if memory lower power feature policy states that it is disabled, VPG memory should still be poweerd on if it is currently disabled when requested. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Charlene Liu authored
[why] need to apply the debug key check for max displayclk. Reviewed-by:
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Xiaojian Du authored
This will add VCN sensor value for SMU 14.0.0. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
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Shashank Sharma authored
The idea behind this patch is to delay the freeing of PT entry objects until the TLB flush is done. This patch: - Adds a tlb_flush_waitlist in amdgpu_vm_update_params which will keep the objects that need to be freed after tlb_flush. - Adds PT entries in this list in amdgpu_vm_ptes_update after finding the PT entry. - Changes functionality of amdgpu_vm_pt_free_dfs from (df_search + free) to simply freeing of the BOs, also renames it to amdgpu_vm_pt_free_list to reflect this same. - Exports function amdgpu_vm_pt_free_list to be called directly. - Calls amdgpu_vm_pt_free_list directly from amdgpu_vm_update_range. V2: rebase V4: Addressed review comments from Christian - add only locked PTEs entries in TLB flush waitlist. - do not create a separate function for list flush. - do not create a new lock for TLB flush. - there is no need to wait on tlb_flush_fence exclusively. V5: Addressed review comments from Christian - change the amdgpu_vm_pt_free_dfs's functionality to simple freeing of the objects and rename it. - add all the PTE objects in params->tlb_flush_waitlist - let amdgpu_vm_pt_free_root handle the freeing of BOs independently - call amdgpu_vm_pt_free_list directly V6: Rebase V7: Rebase V8: Added a NULL check to fix this backtrace issue: [ 415.351447] BUG: kernel NULL pointer dereference, address: 0000000000000008 [ 415.359245] #PF: supervisor write access in kernel mode [ 415.365081] #PF: error_code(0x0002) - not-present page [ 415.370817] PGD 101259067 P4D 101259067 PUD 10125a067 PMD 0 [ 415.377140] Oops: 0002 [#1] PREEMPT SMP NOPTI [ 415.382004] CPU: 0 PID: 25481 Comm: test_with_MPI.e Tainted: G OE 5.18.2-mi300-build-140423-ubuntu-22.04+ #24 [ 415.394437] Hardware name: AMD Corporation Sh51p/Sh51p, BIOS RMO1001AS 02/21/2024 [ 415.402797] RIP: 0010:amdgpu_vm_ptes_update+0x6fd/0xa10 [amdgpu] [ 415.409648] Code: 4c 89 ff 4d 8d 66 30 e8 f1 ed ff ff 48 85 db 74 42 48 39 5d a0 74 40 48 8b 53 20 48 8b 4b 18 48 8d 43 18 48 8d 75 b0 4c 89 ff <48 > 89 51 08 48 89 0a 49 8b 56 30 48 89 42 08 48 89 53 18 4c 89 63 [ 415.430621] RSP: 0018:ffffc9000401f990 EFLAGS: 00010287 [ 415.436456] RAX: ffff888147bb82f0 RBX: ffff888147bb82d8 RCX: 0000000000000000 [ 415.444426] RDX: 0000000000000000 RSI: ffffc9000401fa30 RDI: ffff888161f80000 [ 415.452397] RBP: ffffc9000401fa80 R08: 0000000000000000 R09: ffffc9000401fa00 [ 415.460368] R10: 00000007f0cc0000 R11: 00000007f0c85000 R12: ffffc9000401fb20 [ 415.468340] R13: 00000007f0d00000 R14: ffffc9000401faf0 R15: ffff888161f80000 [ 415.476312] FS: 00007f132ff89840(0000) GS:ffff889f87c00000(0000) knlGS:0000000000000000 [ 415.485350] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 415.491767] CR2: 0000000000000008 CR3: 0000000161d46003 CR4: 0000000000770ef0 [ 415.499738] PKRU: 55555554 [ 415.502750] Call Trace: [ 415.505482] <TASK> [ 415.507825] amdgpu_vm_update_range+0x32a/0x880 [amdgpu] [ 415.513869] amdgpu_vm_clear_freed+0x117/0x250 [amdgpu] [ 415.519814] amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu+0x18c/0x250 [amdgpu] [ 415.527729] kfd_ioctl_unmap_memory_from_gpu+0xed/0x340 [amdgpu] [ 415.534551] kfd_ioctl+0x3b6/0x510 [amdgpu] V9: Addressed review comments from Christian - No NULL check reqd for root PT freeing - Free PT list regardless of needs_flush - Move adding BOs in list in a separate function V10: Added Christian's RB V11: squash in list fix Cc: Christian König <Christian.Koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Felix Kuehling <felix.kuehling@amd.com> Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Acked-by:Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Reviewed-by:
Christian König <Christian.Koenig@amd.com> Tested-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
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- 20 Mar, 2024 24 commits
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lima1002 authored
add new vcn and jpeg msg v2: squash in updates (Alex) v3: rework code for better compat with other smu14.x variants (Alex) Reviewed-by:
lima1002 <li.ma@amd.com> Signed-off-by:
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Hawking Zhang authored
Enable smuio v14_0_2_callbacks Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Hawking Zhang authored
Add smuio callback to get gpu clk counter Signed-off-by:
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Hawking Zhang authored
Add smuio v14_0_2 ip block support Signed-off-by:
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Hawking Zhang authored
v1: Add smuio v14_0_2 register offset and shift masks header files. (Hawking) v2: Update smuio v14_0_2 register offset and shift masks header files to RE2. (Likun) v3: Update smuio v14_0_2 register offset and shift masks header files to RE2.5. (Likun) v4: Clean up smuio v14_0_2 ip headers (Alex) Signed-off-by: -
Yang Wang authored
add umc v12.0.0 deferred error support. Signed-off-by:
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Yang Wang authored
add aca deferred error type support Signed-off-by:
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Xiaojian Du authored
This will add VCN sensor value for SMU 13.0.5. Signed-off-by:
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Tao Zhou authored
Each RAS block has different requirement for gpu reset in poison consumption handling. Add support for mmhub RAS poison consumption handling. v2: remove the mmhub poison support for kfd int v10. Signed-off-by:
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Yang Wang authored
retire unused aca_bank_report data structure. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Cursor update can be pre-empted by a request for setting target flip submission. This causes an issue where we're in the middle of the exit sequence trying to log to DM, but the pre-emption starts another DMCUB command submission that requires being out of idle. The DC lock aqusition can fail, and depending on the DM/OS interface it's possible that the function inserted into this thread must not fail. This means that lock aqusition must be skipped and exit *must* occur. [How] Modify when we consider idle as active. Consider it exited only once the exit has fully finished. Consider it as entered prior to actual notification. Since we're on the same core/thread the cached values are coherent and we'll see that we still need to exit. Once the cursor update resumes it'll continue doing the double exit but this won't cause a functional issue, just a (potential) redundant operation. Reviewed-by:
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Xiaojian Du authored
This will add VCN sensor value for yellow carp. Signed-off-by:
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Candice Li authored
Use helper function instead of umc callback to set EEPROM table version. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
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Aric Cyr authored
This version brings along following fixes: - Clear mpc_tree in init_pipes - Program pixclk according to dcn revision - Add stream clock source to DP DTO params - Enabling urgent latency adjustment for DCN35 - To adjust dprefclk by down spread percentage - Add debug option for idle reg checks - Revert few patches which cause regression - skip forcing odm in minimal transition - Fix noise issue on HDMI AV mute - Enable fast update for DCN314 - Enable 2to1 ODM policy for DCN35 - Fix DCN31 underflow problem - Add the MALL size in the fallback function - Modify coding style/errors and remove redundant codes - Add missing registers and offset Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Anthony Koo authored
- Add a Replay residency mode which only calcuates the entry time based on replay state 0/1 switch. Acked-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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Yang Wang authored
refine aca error cache for umc v12.0 Signed-off-by:
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Yang Wang authored
refine aca error cache for sdma v4.4.2 Signed-off-by:
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Yang Wang authored
refine aca error cache for xgmi v6.4.0 Signed-off-by:
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Tao Zhou authored
Support the query for both gfxhub and mmhub, also replace xcc_id with hub_inst. Signed-off-by:
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Tao Zhou authored
Add it for mmhub v1.8. Signed-off-by:
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Xiaojian Du authored
This will drm/amdgpu: add VCN sensor value for Vangogh. Signed-off-by:
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Samson Tam authored
[Why] During init_pipes, otg master is not initialized. So mpc tree is still configured even if mpc bottom is not active [How] For pipes that have tg enabled, check their mpc tree and clear opp_list if mpc bottom is not active Reviewed-by:
George Shen <george.shen@amd.com> Acked-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Yang Wang authored
refine aca error cache for mmhub v1.8 Signed-off-by:
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Dillon Varone authored
[WHY&HOW] Pixel clock programming should be built per dcn revision, not hardcoded to use dcn20. Reviewed-by:
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